Patents Assigned to Instruments Incorporated
  • Patent number: 12389640
    Abstract: An integrated circuit includes a shallow P-type well (SPW) below a surface of a semiconductor substrate and a shallow N-type well (SNW) below the surface. The SPW forms an anode of a diode and the SNW forms a cathode of the diode. The SNW is spaced apart from the SPW by a well space region; and a thin field relief oxide structure lies over the well space region.
    Type: Grant
    Filed: May 3, 2024
    Date of Patent: August 12, 2025
    Assignee: Texas Instruments Incorporated
    Inventors: Henry Litzmann Edwards, Joseph Maurice Khayat, Archana Venugopal
  • Patent number: 12386405
    Abstract: Embodiments disclosed herein relate to split rail architecture for power supplies in a system, and more particularly, to providing isolation and control of a power supply. In an example, an integrated circuit device is provided that includes a device voltage supply, an input/output (I/O) voltage supply coupled to the device voltage supply, and a level shifter circuit coupled to the I/O voltage supply. The level shifter circuit includes a pair of cross-coupled p-type metal-oxide semiconductor field effect transistors (PMOS transistors), a pair of n-type transistors (NMOS transistors) coupled between the pair of cross-coupled PMOS transistors and a ground connection, and an inverter circuit coupled to the device voltage supply and the level shifter circuit. The level shifter circuit further includes a capacitor coupled to the pair of cross-coupled PMOS transistors and the ground connection and is in parallel with respect to a first one of the pair of NMOS transistors.
    Type: Grant
    Filed: October 31, 2023
    Date of Patent: August 12, 2025
    Assignee: Texas Instruments Incorporated
    Inventors: Ruchi Shankar, Robin O. Hoel, Patrick Seem, Oddgeir Fikstvedt, Jan-Tore Marienborg
  • Patent number: 12388027
    Abstract: An integrated circuit (IC) fabrication flow including a multilevel metallization scheme wherein one or more metal layer members of a scribelane structure are formed according to one or more design constraints. A total thickness of the metal layer members of the scribelane structure along a dicing path may be limited to a threshold value to optimize dicing separation yields in a dicing operation.
    Type: Grant
    Filed: June 6, 2022
    Date of Patent: August 12, 2025
    Assignee: Texas Instruments Incorporated
    Inventors: Jeffrey Alan West, Elizabeth Costner Stewart
  • Patent number: 12379925
    Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream. Once fetched data elements in the data stream are disposed in lanes in a stream head register in the fixed order. Some lanes may be invalid, for example when the number of remaining data elements are less than the number of lanes in the stream head register. The streaming engine automatically produces a valid data word stored in a stream valid register indicating lanes holding valid data. The data in the stream valid register may be automatically stored in a predicate register or otherwise made available. This data can be used to control vector SIMD operations or may be combined with other predicate register data.
    Type: Grant
    Filed: March 25, 2024
    Date of Patent: August 5, 2025
    Assignee: Texas Instruments Incorporated
    Inventors: Joseph Zbiciak, Son H. Tran
  • Patent number: 12382736
    Abstract: An integrated circuit includes a semiconductor substrate with a semiconductor surface layer having a first conductivity type and a top surface, a diode including a buried region within the surface layer, the buried region having an opposite second conductivity type and being spaced apart from the top surface by a portion of the semiconductor surface layer having the first conductivity type, a dielectric layer over the surface layer, and a metal layer located over the dielectric layer and including an aperture extending laterally in a first direction over the semiconductor surface layer and laterally spaced apart from the buried region in a second direction.
    Type: Grant
    Filed: June 29, 2022
    Date of Patent: August 5, 2025
    Assignee: Texas Instruments Incorporated
    Inventors: Henry L. Edwards, Udumbara Wijesinghe, William R. Krenik
  • Patent number: 12381532
    Abstract: An acoustic-wave device includes a first electrode located over a substrate. A piezoelectric film is located over the first electrode and at least partially overlaps the first electrode. A second electrode is located over the piezoelectric film and at least partially overlaps the first electrode and the piezoelectric film. A temperature sensor is located in a same layer level as the first or second electrode. A heater may also be located in a same layer level as the first electrode. A closed-loop system may operate using the temperature sensor and the heater to maintain an operating temperature that provides highly stable operation.
    Type: Grant
    Filed: June 11, 2021
    Date of Patent: August 5, 2025
    Assignee: Texas Instruments Incorporated
    Inventors: Keegan Shaun Martin, Ting-Ta Yen
  • Patent number: 12382658
    Abstract: An integrated circuit includes a first field effect transistor (FET) and a second FET formed in or over a semiconductor substrate and configured to selectively conduct a current between a first circuit node and a second circuit node. The first FET has a first source, a first drain and a first buried layer all having a first conductivity type, and a first gate between the first source and the first drain. The second FET has a second source, a second drain and a second buried layer all having the first conductivity type, and a second gate between the second source and the second drain. A first potential between the first source and the first buried layer is configurable independently from a second potential between the second source and the second buried layer.
    Type: Grant
    Filed: February 28, 2022
    Date of Patent: August 5, 2025
    Assignee: Texas Instruments Incorporated
    Inventors: Henry Litzmann Edwards, Narayana Sateesh Pillai, Gangqiang Zhang, Angelo William Pereira
  • Publication number: 20250246995
    Abstract: A circuit includes a controller configured to control switching of a first transistor and a second transistor in switching converter. The controller includes a compensation loop and a deadtime circuit. The compensation loop is configured to provide a compensation value. The deadtime circuit is configured to determine a deadtime value based on the compensation value. The deadtime value defines an interval between turn-off of the first transistor and turn-on of the second transistor.
    Type: Application
    Filed: January 31, 2024
    Publication date: July 31, 2025
    Applicant: Texas Instruments Incorporated
    Inventors: Hua TANG, Xuemei LU, Zhaofu ZHOU, Pengcheng BAN, Yubo WANG
  • Publication number: 20250247097
    Abstract: A circuit includes a semiconductor substrate, a first ground terminal, a second ground terminal, a driver circuit, a capacitor, a receiver circuit, and a substrate bias circuit. The driver circuit is on the semiconductor substrate. The driver circuit is coupled to the first ground terminal, and has a first output and a second output. The capacitor has a first terminal coupled to the first output of the driver circuit and a second terminal. The receiver circuit is on the semiconductor substrate. The receiver circuit is coupled to the second ground terminal, and has a first input coupled to the second terminal of the capacitor, and a second input coupled to the second output of the driver circuit. The substrate bias circuit has a first input coupled to the first ground terminal, a second input coupled to the second ground terminal, and an output coupled to the semiconductor substrate.
    Type: Application
    Filed: March 29, 2024
    Publication date: July 31, 2025
    Applicant: Texas Instruments Incorporated
    Inventors: Yuan RAO, Sreeram Nasum S, Anthony CALABRIA, Tarunvir SINGH, Ajith Kumar NARAYANASETTY
  • Patent number: 12375094
    Abstract: A system includes a first digital-to-time converter (DTC) adapted to receive a first DTC code and a first clock signal. The first DTC provides an output clock signal. The system includes a calibration DTC adapted to receive a calibration DTC code and a second clock signal. The calibration DTC provides a calibration output signal. The system includes a latch comparator which provides outputs indicative of which of the output clock signal and the calibration output signal is received first. The system includes an average computation module which provides an average value of the outputs of the latch comparator. The system includes a digital controller adapted to receive the average value. The digital controller provides the DTC code and the calibration DTC code.
    Type: Grant
    Filed: December 11, 2023
    Date of Patent: July 29, 2025
    Assignee: Texas Instruments Incorporated
    Inventors: Jayawardan Janardhanan, Yogesh Darwhekar, Subhashish Mukherjee
  • Patent number: 12375127
    Abstract: Universal Serial Bus (USB) repeater circuits and methods of operating the same for communicating data signals from a first pair of data terminals to a second pair of data terminals of the repeater. In a first channel, an amplifier stage in a receiver amplifies a differential signal received at the first pair of data terminals to generate a differential signal at first and second output nodes of the receiver, and a transmitting circuit transmits a differential signal at the second pair of data terminals responsive to the differential signal at the first and second output nodes of the receiver. The receiver includes a hysteresis stage that receives an offset in opposition to the differential signal at the first and second output nodes of the receiver. End-of-packet (EOP) dribble in USB communications in the HS mode is reduced by the offset at the hysteresis stage.
    Type: Grant
    Filed: April 3, 2024
    Date of Patent: July 29, 2025
    Assignee: Texas Instruments Incorporated
    Inventors: Srijan Rastogi, Mayank Garg, Anant Shankar Kamath
  • Patent number: 12372565
    Abstract: An example apparatus includes: calibration circuitry configured to determine a second current at a second terminal of a second impedance circuit based on a first parasitic capacitance, a first impedance value, a third impedance value, a first voltage, and a second voltage; determine a third voltage at a second terminal of a second impedance circuit based on the first parasitic capacitance, a second impedance value, the third impedance value, the second voltage, and the second current; and determine a second parasitic capacitance between the second terminal of the second impedance circuit and the second terminal of a fifth impedance circuit based on the second current, the third voltage, a third current at the second terminal of the fifth impedance circuit, and a fourth voltage at the second terminal of the fifth impedance circuit.
    Type: Grant
    Filed: March 30, 2023
    Date of Patent: July 29, 2025
    Assignee: Texas Instruments Incorporated
    Inventors: Aatish Chandak, Aravind Miriyala, Midhun Raveendran, Anand Hariraj Udupa, Raja Reddy Patukuri, Prabin Krishna Yadav
  • Patent number: 12376370
    Abstract: A method of fabricating an integrated circuit includes forming a first opening having a first width and a second opening having a second width in a first dielectric layer over a silicon substrate. The openings expose the silicon substrate and the exposed silicon substrate is oxidized to form first and second LOCOS structures having a first thickness. A polysilicon layer is formed over the silicon substrate, so that the polysilicon layer fills the first and second openings. A blanket etch of the polysilicon layer is performed to remove at least a portion of the polysilicon layer over the second LOCOS structure while leaving the first LOCOS structure protected by the polysilicon layer. The silicon substrate under the second LOCOS structure is further oxidized such that the second LOCOS structure has a second thickness greater than the first thickness.
    Type: Grant
    Filed: April 11, 2024
    Date of Patent: July 29, 2025
    Assignee: Texas Instruments Incorporated
    Inventors: Abbas Ali, Christopher Scott Whitesell, John Christopher Shriner, Henry Litzmann Edwards
  • Patent number: 12375071
    Abstract: A serial bus re-driver circuit includes an edge detector circuit and a booster circuit. The edge detector circuit is configured to detect a transition of serial bus signal. The booster circuit is coupled to the edge detector circuit, and is configured to switch current to the serial bus signal. The booster circuit includes a leading edge boost pulse generation circuit and a trailing edge boost pulse generation circuit. The leading edge boost pulse generation circuit is configured to switch a first current pulse to the serial bus signal at the transition of the serial bus signal. The trailing edge boost pulse generation circuit is configured to switch a second current pulse to the serial bus signal. The second current pulse is shorter than the first current pulse.
    Type: Grant
    Filed: June 6, 2023
    Date of Patent: July 29, 2025
    Assignee: Texas Instruments Incorporated
    Inventors: Srijan Rastogi, Srikanth Manian
  • Patent number: 12369805
    Abstract: An apparatus to detect a heart rate of a user includes a motion detection circuit configured to generate a motion status signal indicative of a motion status of the user. The apparatus also comprises a filter circuit coupled to the motion detection circuit that is configured to generate a filter circuit output signal based on dynamically variable. The coefficients are dependent on the motion status signal and a first signal received by the filter circuit. The apparatus also comprises a combination circuit coupled to the filter circuit and configured to receive a second signal indicative of the ambient light, the motion of the user, and non-ambient light reflected from the user. The combination circuit is configured to determine a difference between the second signal and the filter circuit output signal to generate a combination circuit output signal.
    Type: Grant
    Filed: December 16, 2020
    Date of Patent: July 29, 2025
    Assignee: Texas Instruments Incorporated
    Inventors: Sarma Sundareswara Gunturi, Jaiganesh Balakrishnan
  • Patent number: 12375070
    Abstract: Embodiments disclosed herein relate to the management of a multi-trim oscillator to provide synchronization across multiple frequencies derived from the multi-trim oscillator without causing spurious pulses of clock output. In one example, a system provides a first clock signal via an oscillator and a second clock signal based on the first clock signal and a divider. The system further receives a first signal that indicates a change in a frequency of the first clock signal from a first frequency to a second frequency. In response to the first signal, the system determines an edge of the second clock signal and provides, at a time based on the edge of the second clock signal, a second signal to the oscillator to cause the change to the second frequency.
    Type: Grant
    Filed: December 20, 2023
    Date of Patent: July 29, 2025
    Assignee: Texas Instruments Incorporated
    Inventors: Gregory North, Sudhakar Surendran, Venkatraman Ramakrishnan
  • Patent number: 12367147
    Abstract: A method is described herein. The method generally includes receiving stream parameters that defines an array, wherein the stream parameters include a first null element count and a second null element count. The method generally includes forming a stream of vectors for the multidimensional array responsive to the stream parameters. The stream of vectors generally includes a vector of null elements at a beginning of the stream of vectors based on the first null element count. The stream of vectors generally includes a null element at a beginning of each vector of the stream of vectors based on the second null element count. The stream of vectors generally includes a set of data distributed across a subset of the stream of vectors. The method generally includes providing the stream of vectors.
    Type: Grant
    Filed: February 6, 2023
    Date of Patent: July 22, 2025
    Assignee: Texas Instruments Incorporated
    Inventors: Asheesh Bhardwaj, Burton Adrik Copeland, Elliott Gurrola, Tim Anderson, William Leven
  • Patent number: 12367150
    Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements. A steam head register stores data elements next to be supplied to functional units for use as operands. The streaming engine stores an early address of next to be fetched data elements and a late address of a data element in the stream head register for each of the nested loops. The streaming engine stores an early loop counts of next to be fetched data elements and a late loop counts of a data element in the stream head register for each of the nested loops.
    Type: Grant
    Filed: July 24, 2023
    Date of Patent: July 22, 2025
    Assignee: Texas Instruments Incorporated
    Inventors: Joseph Zbiciak, Timothy D. Anderson
  • Patent number: 12366877
    Abstract: Examples of bandgap circuits and elements thereof enable generation of an accurate and stable bandgap reference voltage that is not affected by low current gain. An example circuit includes first and second input transistors, each having an emitter to receive a tail current; first and second core transistors, a collector of each coupled to ground; a first lower leg coupled between a first upper leg and the emitter of the first core transistor at a first current input coupled to the base of the first input transistor; a second lower leg coupled between a second upper leg and the emitter of the second core transistor at a second current input coupled to the base of the second input transistor; and a base resistor coupled between the base and collector of the first core transistor. The input transistor pair has a current density ratio that is the same as that of the core transistor pair.
    Type: Grant
    Filed: September 22, 2022
    Date of Patent: July 22, 2025
    Assignee: Texas Instruments Incorporated
    Inventors: Sudheer Gangula, Jerry Doorenbos, Dimitar Trifonov
  • Patent number: 12368414
    Abstract: A method for digital predistortion (DPD) calibration in a wireless communication device is provided that includes transmitting, by transmission circuitry of the wireless communication device, a plurality of pulses, where each pulse corresponds to an amplitude step in a pattern of amplitude steps, where the amplitude steps are separated by silence gaps, receiving each pulse in receiver circuitry of the wireless communication device, generating, by an accumulator component of the wireless communication device, an accumulated sample for each pulse based on a plurality of samples output by the receiver circuitry for the pulse, and computing, by a processor of the wireless communication device, amplitude dependent gain (AM/AM) and amplitude dependent phase shift (AM/PM) values for each accumulated sample.
    Type: Grant
    Filed: January 16, 2024
    Date of Patent: July 22, 2025
    Assignee: Texas Instruments Incorporated
    Inventors: Raghu Ganesan, Harish Ramesh, John Roshan Samuel Chandran, Lakshmi Bala Krishna Manoja Vinnakota