Abstract: A device includes a communication interface, a command processing circuit, a clock synchronization circuit, and a controllable clock source. The command processing circuit has a command input, a reference frequency output, and a reference phase output. The command input is coupled to the communication interface. The clock synchronization circuit has a reference frequency input, a reference phase input, and a frequency control output. The reference frequency output is coupled to the reference frequency input, and the reference phase input coupled to the reference phase output. The clock synchronization circuit includes a frequency synchronization circuit and a phase synchronization circuit. The controllable clock source has a frequency control input and a clock output. The frequency control input is coupled to the frequency control output.

Abstract: An example apparatus includes a first transistor configured to receive an analog voltage signal; a second transistor configured to receive a first control signal, coupled to the first transistor, and coupled to a first terminal; a third transistor configured to receive a second control signal, receive a supply voltage, and coupled to the first terminal; a capacitor coupled to the first terminal and to ground; a fourth transistor configured to receive a third control signal and coupled to the first terminal; a fifth transistor gate configured to receive a bias voltage, coupled to ground, and coupled to the fourth transistor; a sixth transistor coupled to the fourth transistor and to ground; a seventh transistor configured to receive the supply voltage, coupled to the first terminal and to the sixth transistor; and an eighth transistor coupled to the first terminal, to the sixth transistor, and to ground.

Abstract: Using a phase interferometry method which utilizes both amplitude and phase allows the determination and estimation of multipath signals. To determine the location of an object, a signal that contains sufficient information to allow determination of both amplitude and phase, like a packet that includes a sinewave portion, is provided from a master device. A slave device measures the phase and amplitude of the received packet and returns this information to the master device. The slave device returns a packet to the master that contains a similar sinewave portion to allow the master device to determine the phase and amplitude of the received signals. Based on the two sets of amplitude and phase of the RF signals, the master device utilizes a fast Fourier transform or techniques like multiple signal classification to determine the indicated distance for each path and thus more accurately determines a location of the slave device.

Abstract: An electronic circuit for controlling a power switch having a gate input, includes a signal generator configured to generate a gate driver input signal. The gate driver input signal has a first voltage during a first period of time, a second voltage during a second period of time, and toggles between the first voltage and the second voltage during a third period of time. The electronic circuit also includes a gate driver configured to receive the gate driver input signal and to provide a gate driver output signal based on the gate driver input signal. The signal generator is configured to cause the gate driver input signal to toggle during the third period of time such that the gate driver output signal has a third voltage during the second period of time, and an intermediate voltage that is less than the third voltage during the third period of time.

Abstract: Examples of circuitry and systems and methods provide a multi-way configurable amplifier to support various applications. The multi-way configurable amplifier may include a reconfigurable filter that comprises first and second inputs adapted to receive an input signal; a fully differential amplifier (FDA); and first and second reconfigurable resistance-capacitance (RC) networks. The FDA has an inverting input, a non-inverting input, an inverting output, and a non-inverting output. The inverting input is coupled to the first input, and the non-inverting input is coupled to the second input. The first reconfigurable RC network is coupled to the non-inverting output, and the second reconfigurable RC network is selectively couplable to the inverting output. The reconfigurable filter is configurable to enable operation in any of multiple modes including a single-ended mode of operation and a differential mode of operation.

Abstract: In some implementations, a method includes forming first and second fins on a semiconductor substrate. The method further includes diffusing first and second implants into the semiconductor substrate and first and second fins. The method also includes patterning a field plate on the semiconductor substrate. An active device, such as a laterally-diffused metal-oxide semiconductor field effect (LDMOS) transistor can be formed in this way.

Abstract: A distance measurement system includes a light transmitter to generate a modulated light signal, a light sensor to generate measurement signals from reflected light among four quad phase angles with respect to a phase of the generated light signal, and a controller. The controller selects a first set of quad phase angles, and generates first measurement signals at the quad phase angles of the first set. Based on the first measurement signals, the controller computes a first phase angle between the generated light signal and the reflected light signal, generates a second set of quad phase angles based on the first phase angle, and generates second measurement signals at the quad phase angles of the second set. Further, based on the second measurement signals, the controller computes a second phase angle between the generated light signal and the reflected light signal and calculates a distance using the second phase angle.

Abstract: A method includes determining, by a level one (L1) controller, to change a size of a L1 main cache; servicing, by the L1 controller, pending read requests and pending write requests from a central processing unit (CPU) core; stalling, by the L1 controller, new read requests and new write requests from the CPU core; writing back and invalidating, by the L1 controller, the L1 main cache. The method also includes receiving, by a level two (L2) controller, an indication that the L1 main cache has been invalidated and, in response, flushing a pipeline of the L2 controller; in response to the pipeline being flushed, stalling, by the L2 controller, requests received from any master; reinitializing, by the L2 controller, a shadow L1 main cache. Reinitializing includes clearing previous contents of the shadow L1 main cache and changing the size of the shadow L1 main cache.

Abstract: A method includes forming, on a dielectric layer of an integrated circuit, a first layer of a first material, forming, on the first layer, a second layer of a second material, and patterning the second layer to expose the first layer. Via the patterned second layer, the exposed first layer is etched to form protrusion structures of the first layer and the second layer and grooves between adjacent ones of the protrusion structures. The method also includes forming a graphitic carbon layer on at least part of the second layer of the protrusion structures, and depositing carbon nanotubes into the grooves between the adjacent ones of the protrusion structures.

Abstract: In response to a rising edge on an input pulse width modulation (PWM) signal, a method includes starting a first counter, resetting a second counter, and forcing a second PWM signal to a logic low level. In response to the first counter reaching a first match value, the method includes asserting a rising edge on a first PWM signal. In response to a falling edge on the input PWM signal, the method further includes causing a falling edge of the first PWM signal, resetting the first counter, and starting the second counter. In response to the second counter reaching a second match value, the method includes asserting a rising edge of the second PWM signal.

Abstract: A temperature dependent correction circuit includes a first supply source, a second supply source, a rectifying circuit, and a reference. The first supply source is configured to supply a first signal that varies with temperature along a first constant or continuously variable slope. The second supply source is configured to supply a second signal that varies with temperature along a second constant or continuously variable slope. The rectifying circuit is configured to receive the first and second signal, rectify the first signal to produce a first rectified signal, and add the first rectified signal to the second signal to produce a correction signal. The reference is configured to receive the correction signal.

Abstract: In some examples, an apparatus includes an isolating transformer and a grounding circuit. The isolating transformer has first and second coils separated by an isolation barrier, the first coil having first and second terminals. The grounding circuit is coupled to the first and second terminals. The grounding circuit is configured to couple the first and second terminals to a ground terminal during a first time period. The grounding circuit is also configured to decouple the first and second terminals from the ground terminal during a second time period.

Abstract: A caching system including a first sub-cache, and a second sub-cache, coupled in parallel with the first cache, for storing cache data evicted from the first sub-cache and write-memory commands that are not cached in the first sub-cache, and wherein the second sub-cache includes: color tag bits configured to store an indication that a corresponding cache line of the second sub-cache storing write miss data is associated with a color tag, and an eviction controller configured to evict cache lines of the second sub-cache storing write-miss data based on the color tag associated with the cache line.

Abstract: A receiver circuit includes a feedback loop including a device. The receiver circuit also includes a register and a sequencer. The sequencer is configured to, responsive to an error signal being below a threshold value, cause the register to store a value indicative of the state of the feedback loop. The sequencer is also configured to cause the feedback loop to transition to a lower power state, and, responsive to a detected wake-up event, cause the previously stored value indicative of the state of the feedback loop to be loaded from the register into the device and enable the feedback loop.

Abstract: A circuit includes an operational amplifier and a resistor network coupled to an output of the operational amplifier. The resistor network includes a first set of resistors coupled between the output of the operational amplifier and a first node of the resistor network, wherein the resistors of the first set are electrically connected in series with each other, a second set of resistors coupled between the first node and a second node of the resistor network, wherein the resistors of the second set are electrically connected in series with each other and include a first number of resistors, a third set of resistors coupled between the second node and a third node of the resistor network, wherein the third node is coupled to a first voltage, and wherein the resistors of the third set are electrically connected in parallel with each other and include a second number of resistors, and a resistor coupled between the first node and the second node and arranged in parallel with the second set of resistors.

Abstract: An apparatus includes a charge transfer circuit, a control circuit, and a processing circuit. The charge transfer circuit has a first terminal, a second terminal, a third terminal, and a control input. The control circuit has a control output coupled to the control input. The processing circuit has a first input, a second input, and an output. The processing circuit is configured to receive a first signal at the first input and receive a second signal at the second input. The first signal represents a current through the charge transfer circuit. The second signal represents at least one of a first voltage between the first and second terminals or a second voltage between the second and third terminals. The processing circuit is also configured to provide a third signal based on the first and second signals at the output.

Abstract: Disclosed herein are systems and methods for executing multiple instruction set architectures (ISAs) on a singular processing unit. In an implementation, a processor that includes a first decoder, a second decoder, instruction fetch circuitry, and instruction dispatch circuitry is configured to execute two separate instruction set architectures. In an implementation, the instruction fetch circuitry is configured to fetch instructions from an associated memory. In an implementation the instruction dispatch circuitry is coupled to the instruction fetch circuitry, the first decoder, and the second decoder and is configured to route instructions associated with a first ISA to the first decoder, and route instructions associated with a second ISA to the second decoder.

Abstract: An example apparatus includes: controller circuitry configured to: provide switch signals to capacitive digital to analog converter (C-DAC) circuitry, the C-DAC circuitry including switches; configuring the switches into a third configuration begin an Auto Zero (AZ) phase with a third switch in a closed state; configuring the switches into a fourth configuration to repeat the transition of the third switch to the open state corresponding to a first configuration; configuring the switches into a fifth configuration to repeat the transition of a first switch and a second switch to the open state corresponding to a second configuration; configuring the switches into a sixth configuration to repeat the transition of the third switch to the closed state corresponding to a second configuration; and performing an AZ decision with the switches in the sixth configuration.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed for multi-banked victim cache with dual datapath. An example cache system includes a storage element that includes banks operable to store data, ports operable to receive memory operations in parallel, wherein each of the memory operations has a respective address, and a plurality of comparators coupled such that each of the comparators is coupled to a respective port of the ports and a respective bank of the banks and is operable to determine whether a respective address of a respective memory operation received by the respective port corresponds to the data stored in the respective bank.

Abstract: A controller area network including one or more first network nodes biased from a first power supply voltage, and a second network node biased from a second, lower, power supply voltage. The second network node includes a transmitter driving a differential voltage onto bus lines to communicate a dominant bus state at a second dominant state common mode voltage, a receiver coupled to the bus lines, sense circuitry to sense a common mode voltage at the bus lines, and control circuitry to control a recessive state common mode voltage in response to the sensed dominant state common mode voltage.