Abstract: In accordance with the invention, a testing circuit formed on the integrated circuit is presented. A testing circuit according to the present invention is coupled to a scan path circuit and includes an input circuit coupled to a parameter testing circuit and an output driver coupled to the parameter testing circuit. Embodiments of the parameter testing circuit can include circuits for testing process, device, and circuit characteristics of the integrated circuit. Further, some embodiments of the testing circuit can be included in a scan path system where sequences of various testing circuits are included. Further, test parameters obtained from the parameter testing circuits can be utilized to adjust operating parameters of the integrated circuit.

Abstract: A cache memory method and corresponding system for two-dimensional data processing, and in particular, two-dimensional image processing with simultaneous coordinate transformation is disclosed. The method uses a wide and fast primary cache memory (PCM) and a deep secondary cache memory (SCM), each with multiple banks to access data simultaneously. A dedicated pre-fetching logic is used to obtain pixel data from an external memory upon receiving control parameters from an external processor system (PU1), and to store that data in the PCM based on a secondary control queue. The data are then prepared in specific block sizes and in specific format, and then stored in the PCM based on optimally sized pre-fetching primary control queue. The prepared data are then read by another external processor system (PU2) for processing. The cache control logic ensures the coherency of data and control parameters at the input of the PU2.

Abstract: A method and circuit for generating a signal to synchronize DQ data transfer in memory interface design is presented. The presented method includes receiving a strobe signal having a preamble period before and post-amble period after data transfer burst synchronization signal edge transitions, determining a timing location of the strobe signal preamble period, determining a timing location of the strobe signal post-amble period, and generating a clean strobe signal that tracks the data transfer burst synchronization edge transitions of the strobe signal after the strobe signal preamble begins and before the strobe signal post-amble ends based on the respective determined timing locations of the strobe signal preamble and post-amble periods. In this manner, DQ data transfer may be synchronized according to the burst synchronization signal edge transitions and errors caused by strobe signal level jitter during the preamble and post-amble periods are reduced.

Abstract: A clock generator includes a phase-lock loop for generating an output clock signal based on a reference clock signal. The phase-lock loop includes a charge pump, a low-pass filter, and a self-bias circuit. The low-pass filter generates a bias voltage and the self-bias circuit generates a charge current based on the bias voltage. The charge pump generates an output based on the charge current to maintain a constant open-loop bandwidth of the phase-lock loop.

Abstract: In accordance with the invention, a driver circuit is described that permits a single thin gate oxide process to be utilized where a dual oxide process may normally be necessary. Circuits employing only thin gate oxide devices are used as the design basis for a single product with a single set of tooling and manufacturing process to operate within the same timing specifications for a core voltage output drive as well as for a higher system drive.

Abstract: In accordance with the invention, a testing circuit formed on the integrated circuit is presented. A testing circuit according to the present invention includes an input circuit coupled to a parameter testing circuit and an output driver coupled to the parameter testing circuit. Embodiments of the parameter testing circuit can include circuits for testing process, device, and circuit characteristics of the integrated circuit. Further, some embodiments of the testing circuit can be included in a scan path system where sequences of various testing circuits are included. Further, test parameters obtained from the parameter testing circuits can be utilized to adjust operating parameters of the integrated circuit.

Abstract: A method for forming CMOS devices on a semiconductor substrate is disclosed in which gate structures are formed within both the core region and the non-core region of the semiconductor substrate. The gate structures include a gate dielectric layer and a gate film stack that includes a conductive layer and an overlying hard mask. The hard mask is then removed from the gate structures in the non-core region. A salicide process is then performed so as to form a silicide layer in the non-core region. A barrier layer is formed that extends over the core region and a pre-metal dielectric film is formed that extends over the barrier layer. A selective etch process is performed so as to form self-aligned contact openings that extend through the pre-metal dielectric film and through the barrier layer in the core region. These openings are then filled with conductive material to form self-aligned contacts in the core region.

Abstract: An audio system includes a CODEC audio jack having left and right audio ports and a jack sense circuit. The jack sense circuit includes left and right amplifiers and a cross-drive impedance sensing circuit. This cross-drive impedance sensing circuit, which is electrically coupled to the left and right audio ports and the left and right amplifiers, detects the resistances of left and right output loads in order to determine characteristics of a device connected to the CODEC audio jack. The cross-drive impedance circuit is configured to measure a resistance of a left output load electrically coupled to the left audio port, in response to a “right” test signal generated by the right amplifier, and is further configured to measure a resistance of a right output load electrically coupled to the right audio port in response to a “left” test signal generated by the left amplifier.

Abstract: A weighted round-robin scheduler includes a round-robin table that stores a plurality of cycle link lists. Each cycle link list includes a head flow identification (FLID) value identifying a first flow of the cycle link list, and a tail FLID value identifying a last flow of the cycle link list. A flow table is provided having a plurality of flow table entries. Each flow table entry is associated with a corresponding flow. Each flow table entry stores a parameter that identifies the weight assigned to the associated flow. A packet queue is associated with each flow table entry, wherein each packet queue is capable of storing a plurality of packets. The weighted round-robin scheduler also includes an idle cycle register having an idle cycle entry corresponding with each of the cycle link lists, wherein each idle cycle entry identifies the corresponding cycle link list as active or idle.

Abstract: A method and apparatus for generic interface, packet cut-through, overbooking, queue concatenation, and logical identification priority for a System Packet Interface device have been disclosed.

Abstract: A clock generator includes a clock circuit and a voltage-controlled oscillator in a phase-locked loop. The clock circuit monitors input clock signals and selects one of the input clock signals based on characteristics of the input clock signals. The voltage-controlled oscillator generates a reference clock signal based on the selected clock signal. The clock circuit also includes synthesizers for generating clock signals, each of which has a frequency being a non-integer multiple of a frequency of the reference clock signal. Additionally, the clock circuit individually offsets the clock signals generated by the synthesizers relative to the reference clock signal. The clock generator is capable of switching the input clock signal during operation of the clock generator while maintaining the reference clock signal. Further, the clock generator is programmable to control operation of the clock circuit.

Abstract: A data output circuit includes a plurality of clocked data output buffers, each of which drives a data output thereof responsive to a clock signal and an adjustable multiphase clock signal generator that generates a plurality of clock signals of different phases and that is operative to shift the plurality of clock signals relative to a reference clock signal responsive to a first control signal. The data output circuit further includes a clock signal selector that selectively applies the plurality of clock signals to the data output buffers responsive to a second control signal. The adjustable multiphase clock signal generator may include, for example, a control loop, such as a phase locked loop or a delay locked loop, which selectively feeds back one of the plurality of clock signals responsive to the first control signal.

Abstract: Core clock alignment circuits include a serial-in parallel-out (SIPO) data processing circuit, which is configured to generate a plurality of lanes of deserialized data in response to a corresponding plurality of lanes of serialized data. The SIPO data processing circuit is further configured to generate a plurality of recovered clock signals from corresponding ones of the plurality of lanes of serialized data. These recovered clock signals may be out-of-phase relative to each other. The devices also include a plurality of lane FIFOs, which are configured to receive respective ones of the plurality of lanes of deserialized data and respective ones of the plurality of recovered clock signals at write ports thereof. A core clock alignment circuit is provided, which may be electrically coupled to the plurality of lane FIFOs.

Abstract: Consistent with the present invention, there is provided a circuit for extracting a common mode voltage of an input signal. The device may include an operational amplifier having an output, at least one negative input and at least one positive input, a first transistor, and a second transistor. A terminal of the first transistor may be coupled to the output of the operational amplifier. A terminal of the second transistor may be coupled to a terminal of the first transistor and the at least one positive input of the operational amplifier to create a negative feedback loop. The device may further include a common mode output, wherein the negative feedback loop extracts the common mode voltage of the input signal, the common mode voltage of the input signal being output at the common mode output. The device consistent with the present invention may provide the common mode voltage of the input signal without using any resistors, and while only occupying a small die area.

Abstract: A memory system includes a plurality of memory blocks, each having a dedicated local arithmetic logic unit (ALU). A data value having a plurality of bytes is stored such that each of the bytes is stored in a corresponding one of the memory blocks. In a read-modify-write operation, each byte of the data value is read from the corresponding memory block, and is provided to the corresponding ALU. Similarly, each byte of a modify data value is provided to a corresponding ALU on a memory data bus. Each ALU combines the read byte with the modify byte to create a write byte. Because the write bytes are all generated locally within the ALUs, long signal delay paths are avoided. Each ALU also generates two possible carry bits in parallel, and then uses the actual received carry bit to select from the two possible carry bits.

Abstract: An apparatus is provided for detecting the loss of an input clock signal for a phase-locked loop (PLL). The apparatus includes a time delay circuit, a first frequency divider and a digital logic circuit. The time delay circuit receives the input clock signal and outputs a first time-delayed clock signal. The first frequency divider receives an input signal from an internal clock of the PLL and outputs a clock signal having the same frequency or a lower frequency than that of the time-delayed clock signal. The digital logic circuit that receives the first frequency divider output signal and the first time-delayed clock signal and outputs a signal indicating the loss of the input clock signal if there is no first time-delayed clock signal for a cycle of the first frequency divider output signal.

Abstract: A low power logic output buffer includes first and second logic gates, each having an input and an output. The input of the first logic gate receives a first logic signal, and the input of the second logic gate receives a second logic signal. The buffer includes first, second, third and fourth n-type metal oxide semiconductor (NMOS). The buffer also includes first and second bias switching NMOS. The first bias switching NMOS is coupled between the source of the third NMOS and ground, and the gate of the first bias switching NMOS is coupled to the output of the first logic gate. The second bias switching NMOS is electrically coupled between the source of the fourth NMOS and ground, and the gate of the second bias switching NMOS is coupled to the output of the second logic gate.

Abstract: A novel method for scanning bit parity in a memory array, and a circuit for implementing it, are disclosed. In a memory array that has one or more rows of memory cells, the method for checking data parity includes storing a plurality of data bits in the memory cells, scanning a row of memory cells independently of a memory read operation to ascertain the stored data bits; and determining parity for the row of memory cells by the results of the scanning. The method is accomplished by means of a dedicated parity scanning circuit.

Abstract: A method and apparatus for ground bounce and power supply bounce detection in devices have been disclosed. In one case one input to a differential amplifier is coupled to a reference voltage and another input to the differential amplifier is coupled to a measurement point and the output of the differential amplifier is coupled through a diode to a sample and hold circuit which is coupled to an analog to digital converter.

Abstract: A die seal structure for sealing integrated circuit devices formed on a semiconductor substrate. The die seal structure includes a die seal and a junction diode. The die seal only connects to the semiconductor substrate through the junction diode, thereby reducing noise coupling through the die seal. In another aspect of the present invention the die seal structure includes a die seal and a bipolar structure. In this embodiment the die seal only connects to the semiconductor substrate through the bipolar structure.