Patents Assigned to Intermolecular, Inc.
  • Patent number: 10364497
    Abstract: Embodiments provided herein describe systems and method for processing substrates. A substrate is provided. A showerhead is positioned above the substrate. The showerhead includes a plurality of injection ports, at least one isolation channel, and at least one exhaust port on a bottom surface thereof. The at least one isolation channel separates the plurality of injection ports into two or more sections. The at least one exhaust port is positioned within the at least one isolation channel. The plurality of injection ports are not in fluid communication with the at least one exhaust port within the showerhead. At least one processing fluid is caused to be delivered from the plurality of injection ports onto the substrate. At least some of the at least one processing fluid is caused to be removed from the substrate through the at least one exhaust port.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: July 30, 2019
    Assignee: INTERMOLECULAR, INC.
    Inventors: Bernardo Donoso, Karl Littau, Lawrence D. Bartholomew
  • Publication number: 20180277289
    Abstract: Provided are inverse phase allotrope rare earth (IPARE) magnets, methods of forming thereof, and applications of IPARE magnets. Unlike conventional samarium-cobalt magnets, IPARE magnets maintain their hexagonal lattice structures over a range of equiatomic compositions, such as when concentrations of different elements are within 10 atomic % of each other. An IPARE magnet may comprise cobalt, iron, copper, nickel, and samarium and a concentration of cobalt may be between 17-27 atomic %. An IPARE magnet may be substantially free from zirconium and/or titanium. An IPARE magnet may be formed by quenching a molten mixture of its components. The quenching may be performed in a magnetic field. After quenching, the IPARE magnet may be machined. Furthermore, IPARE magnets may be used as a structural element, e.g. in an electric motor.
    Type: Application
    Filed: October 12, 2017
    Publication date: September 27, 2018
    Applicant: Intermolecular, Inc.
    Inventor: Abraham Anapolsky
  • Publication number: 20180198064
    Abstract: Provided are novel compositions of current compliance layers (CCLs) as well as novel methods of fabricating such CCLs and novel architectures of arranging CCLs and memory cells in memory arrays. A CCL may comprise one of sulfur (S), selenium (Se), and tellurium (Te). The CCL may further comprise one of germanium (Ge) and silicon (Si). CCLs may be fabricated as amorphous structure and remain amorphous when heated to 400° C. or 450° C. and above. In some embodiments, CCLs have crystallization temperatures of greater than 400° C. and, in some embodiments, glass transition temperatures of greater than 400° C. CCLs may be fabricated using atomic layer deposition (ALD) as a nanolaminate of layers having different compositions. The composition, number, and arrangement of the layers in the nanolaminate is specifically selected to yield a desired composition of CCL.
    Type: Application
    Filed: January 5, 2018
    Publication date: July 12, 2018
    Applicant: Intermolecular, Inc.
    Inventors: Tony Chiang, Sergey V Barabash, Karl Littau, Vijay Kris Narasimhan, Stephen Weeks
  • Patent number: 9831100
    Abstract: Provided are methods for fabricating transistors using a gate last approach. These methods involve etching of titanium nitride and titanium carbide structures while preserving high k-dielectric structures. The titanium carbide structures may also include aluminum. Etching may be performed in one or more etching solutions, each including hydrogen peroxide. Titanium nitride and titanium carbide structures can be etched simultaneously (non-selectively) in the same etching solution that also includes hydrochloric acid, in addition to hydrogen peroxide, and maintained at about 25° C. and 85° C. In some embodiments, titanium nitride structures and titanium carbide structures may be etched separately (selectively) in different operations and using different etching solutions. The titanium nitride structures may be etched in a diluted hydrogen peroxide solution maintained at about 25° C. and 85° C.
    Type: Grant
    Filed: June 24, 2014
    Date of Patent: November 28, 2017
    Assignees: Intermolecular, Inc., International Business Machines
    Inventors: John Foster, Sean Lin, Muthumanickam Sankarapandian, Ruilong Xie
  • Patent number: 9790127
    Abstract: Low emissivity panels can include a separation layer of Zn2SnOx between multiple infrared reflective stacks. The low emissivity panels can also include NiNbTiOx as barrier layer. The low emissivity panels have high light to solar gain, color neutral, together with similar observable color before and after a heat treatment process.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: October 17, 2017
    Assignees: INTERMOLECULAR, INC., Guardian Glass, LLC
    Inventors: Guowen Ding, Jeremy Cheng, Tong Ju, Minh Huu Le, Phil Lingle, Daniel Schweigert, Zhi-Wen Wen Sun, Guizhen Zhang
  • Patent number: 9786368
    Abstract: Provided are memory cells, such as resistive random access memory (ReRAM) cells, each cell having multiple metal oxide layers formed from different oxides, and methods of manipulating and fabricating these cells. Two metal oxides used in the same cell have different dielectric constants, such as silicon oxide and hafnium oxide. The memory cell may include electrodes having different metals. Diffusivity of these metals into interfacing metal oxide layers may be different. Specifically, the lower-k oxide may be less prone to diffusion of the metal from the interfacing electrode than the higher-k oxide. The memory cell may be formed to different stable resistive levels and then resistively switched at these levels. Each level may use a different switching power. The switching level may be selected a user after fabrication of the cell and in, some embodiments, may be changed, for example, after switching the cell at a particular level.
    Type: Grant
    Filed: November 24, 2014
    Date of Patent: October 10, 2017
    Assignees: Intermolecular, Inc., Kabushiki Kaisha Toshiba, SanDisk 3D LLC
    Inventors: Yun Wang, Federico Nardi
  • Patent number: 9761800
    Abstract: Methods for producing RRAM resistive switching elements having reduced forming voltage include preventing formation of interfacial layers, and creating electronic defects in a dielectric film. Suppressing interfacial layers in an electrode reduces forming voltage. Electronic defects in a dielectric film foster formation of conductive pathways.
    Type: Grant
    Filed: June 23, 2014
    Date of Patent: September 12, 2017
    Assignee: Intermolecular, Inc.
    Inventors: Prashant B. Phatak, Ronald J. Kuse, Jinhong Tong
  • Publication number: 20170233868
    Abstract: Embodiments provided herein describe systems and method for processing substrates. A substrate is provided. A showerhead is positioned above the substrate. The showerhead includes a plurality of injection ports, at least one isolation channel, and at least one exhaust port on a bottom surface thereof. The at least one isolation channel separates the plurality of injection ports into two or more sections. The at least one exhaust port is positioned within the at least one isolation channel. The plurality of injection ports are not in fluid communication with the at least one exhaust port within the showerhead. At least one processing fluid is caused to be delivered from the plurality of injection ports onto the substrate. At least some of the at least one processing fluid is caused to be removed from the substrate through the at least one exhaust port.
    Type: Application
    Filed: February 8, 2017
    Publication date: August 17, 2017
    Applicant: Intermolecular, Inc.
    Inventors: Bernardo Donoso, Karl Littau, Lawrence D. Bartholomew
  • Patent number: 9722049
    Abstract: Embodiments described herein provide method for forming crystalline indium-gallium-zinc oxide (IGZO). A substrate is provided. A seed layer is formed above the substrate. The seed layer has a crystalline structure that is substantially dominant along the c-axis. An IGZO layer is formed above the seed layer. The seed layer may include zinc oxide. A stack of alternating seed layers and IGZO layers may be formed.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: August 1, 2017
    Assignees: Intermolecular, Inc., LG Display Co., Ltd.
    Inventors: Sang Lee, Khaled Ahmed, Youn-Gyoung Chang, Min-Cheol Kim, Minh Huu Le, Kwon-Sik Park, Woosup Shin
  • Patent number: 9703024
    Abstract: Disclosed herein are systems, methods, and apparatus for forming low emissivity panels that may include a substrate and a reflective layer formed over the substrate. The low emissivity panels may further include a top dielectric layer formed over the reflective layer such that the reflective layer is formed between the top dielectric layer and the substrate. The top dielectric layer may include a ternary metal oxide, such as zinc tin aluminum oxide. The top dielectric layer may also include aluminum. The concentration of aluminum may be between about 1 atomic % and 15 atomic % or between about 2 atomic % and 10 atomic %. An atomic ratio of zinc to tin in the top dielectric layer may be between about 0.67 and about 1.5 or between about 0.9 and about 1.1.
    Type: Grant
    Filed: November 9, 2016
    Date of Patent: July 11, 2017
    Assignees: Intermolecular Inc., Guardian Industries Corp.
    Inventors: Guizhen Zhang, Brent Boyce, Jeremy Cheng, Guowen Ding, Muhammad Imran, Daniel Schweigert, Yongli Xu
  • Publication number: 20170186935
    Abstract: Provided are superconducting circuits and, more specifically, methods of forming such circuits. A method may involve forming a silicon-containing low loss dielectric (LLD) layer over a metal electrode such that metal carbides at the interface of the LLD layer and electrode. The LLD layer may be formed using chemical vapor deposition (CVD) at a temperature of less than about 500° C. At such a low temperature, metal silicides may not form even though silicon containing precursors may come in contact with metal of the electrode. Silicon containing precursors having silane molecules in which two silicon atoms bonded to each other (e.g., di-silane and tri-silane) may be used at these low temperatures. The LLD layer may include amorphous silicon, silicon oxide, or silicon nitride, and this layer may directly interface one or more metal electrodes. The thickness of LLD layer may be between about 1,000 Angstroms and 10,000 Angstroms.
    Type: Application
    Filed: December 29, 2015
    Publication date: June 29, 2017
    Applicant: Intermolecular, Inc.
    Inventors: Joseph Anthony Bonetti, Frank Greer, Wenxian Zhu
  • Patent number: 9680092
    Abstract: Provided are hybrid electrodes comprising base structures and plugs disposed within the base structures. Also provided are selector elements comprising such hybrid electrodes and memory arrays with selector elements used for addressing individual memory cells. Specifically, the base structure and plug of a hybrid electrode have different compositions but both interface the same dielectric of the selector element. This design allows anti-parallel diode and other configurations with a very few components. The base structure and plug may have different dopants, different stoichiometry of the same alloy, or formed from completely different materials. The interfacing surface portions of a hybrid electrode may have different sizes. A combination of these surface portions (e.g., areas, surface conditions) and materials (e.g., compositions) can be used for tuning operating characteristics of selector elements using such hybrid electrodes.
    Type: Grant
    Filed: August 2, 2016
    Date of Patent: June 13, 2017
    Assignee: Intermolecular, Inc.
    Inventors: Federico Nardi, Mark Clark
  • Publication number: 20170117282
    Abstract: Embodiments provided herein describe capacitor stacks and methods for forming capacitor stacks. A first electrode is formed above a substrate. A dielectric layer is formed above the first electrode. The dielectric layer includes zirconium. A second electrode is formed above the dielectric layer. At least one of the first electrode and the second electrode includes iridium.
    Type: Application
    Filed: October 25, 2016
    Publication date: April 27, 2017
    Applicant: Intermolecular, Inc.
    Inventors: Monica S. Mathur, Randall Higuchi, Thong Quang Ngo, Sandip Niyogi, Prashant Phatak
  • Publication number: 20170104031
    Abstract: Provided are selector elements with active components comprising insulating matrices and mobile ions disposed within these insulating matrices. Also provided are methods of operating such selector elements. The insulating matrices and mobile ions may be formed from different combinations of materials. For example, the insulating matrix may comprise amorphous silicon or silicon oxide, while mobile ions may be silver ions. In another example, the active component comprises copper and germanium, selenium, or tellerium, e.g., Se61Cu39, Se67Cu33, or Se56Cu44. The active component may be a multilayered structure with a variable composition throughout the structure. For example, the concentration of mobile ions may be higher in a center of the structure, away from the electrode interfaces. In some embodiments, outer layers may be formed from Ge33Se24Cu47, while the middle layer may be formed from Ge47Se29Cu24.
    Type: Application
    Filed: October 6, 2016
    Publication date: April 13, 2017
    Applicant: Intermolecular, Inc.
    Inventors: Mark Clark, Prashant Phatak, Charlene Chen, Ashish Bodke, Salil Mujumdar, Federico Nardi, Satbir Kahlon, Sergey V. Barabash, Feihu Wang
  • Patent number: 9620205
    Abstract: A resistive switching memory device can include three or more electrodes interfacing a switching layer, including a top electrode, a bottom electrode, and a side electrode. The top and bottom electrodes can be used for forming conductive filaments and for reading the memory device. The side electrode can be used to control the resistance state of the switching layer.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: April 11, 2017
    Assignee: Intermolecular, Inc.
    Inventors: Federico Nardi, Sergey Barabash, Yun Wang
  • Patent number: 9607904
    Abstract: ALD of HfxAlyCz films using hafnium chloride (HfCl4) and Trimethylaluminum (TMA) precursors can be combined with post-deposition anneal processes and ALD liners to control the device characteristics in high-k metal-gate devices. Variation of the HfCl4 pulse time allows for control of the Al % incorporation in the HfxAlyCz film in the range of 10-13%. Combinatorial process tools can be employed for rapid electrical and materials characterization of various materials stacks. The effective work function (EWF) in metal oxide semiconductor capacitor (MOSCAP) devices with the HfxAlyCz work function layer coupled with ALD deposited HfO2 high-k gate dielectric layers was quantified to be mid-gap at ˜4.6 eV. Thus, HfxAlyCz is a promising metal gate work function material allowing for the tuning of device threshold voltages (Vth) for anticipated multi-Vth integrated circuit (IC) devices.
    Type: Grant
    Filed: December 2, 2013
    Date of Patent: March 28, 2017
    Assignees: Intermolecular, Inc., GLOBALFOUNDRIES, INC.
    Inventors: Albert Sanghyup Lee, Paul Besser, Kisik Choi, Edward L Haywood, Hoon Kim, Salil Mujumdar
  • Publication number: 20170084643
    Abstract: Embodiments provided herein describe storage capacitors for active matrix displays and methods for making such capacitors. A substrate is provided. A bottom electrode is formed above the substrate. A dielectric layer is formed above the bottom electrode. A top electrode is formed above the dielectric layer. A layer including an amorphous or crystalline material may be formed between the dielectric layer and the top electrode. The bottom electrode may have a thickness of at least 1000 ?, be formed in a gaseous environment of at least 95% argon, and/or not undergo an annealing process before the formation of a dielectric layer above the bottom electrode. The dielectric layer may include a nitrided high-k dielectric material.
    Type: Application
    Filed: September 14, 2016
    Publication date: March 23, 2017
    Applicant: Intermolecular, Inc.
    Inventors: Gaurav Saraf, Howard Lin, Prashant Phatak, Sang Lee, Minh Huu Le, Hieu Pham, Congwen Yi
  • Publication number: 20170084680
    Abstract: Embodiments provided herein describe methods and systems for forming high-k dielectric materials, as well as devices that utilize such materials. A property of a high-k dielectric material is selected. A value of the selected property of the high-k dielectric material is selected. A chemical composition of the high-k dielectric material is selected from a plurality of chemical compositions of the high-k dielectric material. The selected chemical composition of the high-k dielectric material includes an amount of nitridation associated with the selected value of the selected property of the high-k dielectric material. The high-k dielectric material is formed with the selected chemical composition.
    Type: Application
    Filed: September 14, 2016
    Publication date: March 23, 2017
    Applicant: Intermolecular, Inc.
    Inventors: Howard Lin, Gaurav Saraf, Kiet Vuong
  • Patent number: 9593414
    Abstract: Amorphous silicon (a-Si) is hydrogenated for use as a dielectric (e.g., an interlayer dielectric) for superconducting electronics. A hydrogenated a-Si layer is formed on a substrate by CVD or sputtering. The hydrogen may be integrated during or after the a-Si deposition. After the layer is formed, it is first annealed in an environment of high hydrogen chemical potential and subsequently annealed in an environment of low hydrogen chemical potential. Optionally, the a-Si (or an H-permeable overlayer, if added) may be capped with a hydrogen barrier before removing the substrate from the environment of low hydrogen chemical potential.
    Type: Grant
    Filed: December 31, 2013
    Date of Patent: March 14, 2017
    Assignees: Intermolecular, Inc., Northrop Grumman Systems Corporation
    Inventors: Sergey Barabash, Chris Kirby, Dipankar Pramanik, Andrew Steinbach
  • Publication number: 20170062524
    Abstract: Provided are hybrid electrodes comprising base structures and plugs disposed within the base structures. Also provided are selector elements comprising such hybrid electrodes and memory arrays with selector elements used for addressing individual memory cells. Specifically, the base structure and plug of a hybrid electrode have different compositions but both interface the same dielectric of the selector element. This design allows anti-parallel diode and other configurations with a very few components. The base structure and plug may have different dopants, different stoichiometry of the same alloy, or formed from completely different materials. The interfacing surface portions of a hybrid electrode may have different sizes. A combination of these surface portions (e.g., areas, surface conditions) and materials (e.g., compositions) can be used for tuning operating characteristics of selector elements using such hybrid electrodes.
    Type: Application
    Filed: August 2, 2016
    Publication date: March 2, 2017
    Applicant: Intermolecular, Inc.
    Inventors: Federico Nardi, Mark Clark