Abstract: Embodiments provided herein describe low-e panels and methods for forming low-e panels. A transparent substrate is provided. A reflective layer is formed above the transparent substrate. A metal oxide layer is formed between the transparent substrate and the reflective layer. A base layer is formed between transparent substrate and the metal oxide layer. The base layer has a first refractive index. A dielectric layer is formed between the base layer and the metal oxide layer. The dielectric layer has a second refractive index.

Abstract: X-ray fluorescence (XRF) monitoring of characteristic peaks while etching thin-film layers can reveal coverage defects and thickness nonuniformity in the top film. To measure coverage and uniformity while screening candidate layer materials and processes, the candidate layers may be formed above an underlayer of a different composition. A wet etchant that selectively etches the underlayer faster than the candidate layer is applied to the candidate layer, and the XRF spectrum is monitored. Pinholes, cracks, islands, and nonuniform thickness in the candidate layer produce characteristic features in the time-dependent behavior of XRF peaks from the underlayer and/or the candidate layer. “Etch/XRF” tests can be used to rapidly and objectively identify the most uniform contiguous candidate layers to advance to further screening or production. XRF may also be calibrated against a known thickness indicator to detect the approach of a desired endpoint in an etch process.

Abstract: Embodiments of the invention generally include a method of forming a nonvolatile memory device that contains a resistive switching memory element that has an improved device switching performance and lifetime, due to the addition of a current limiting component disposed therein. In one embodiment, the current limiting component comprises at least one layer of resistive material that is configured to improve the switching performance and lifetime of the formed resistive switching memory element. The electrical properties of the formed current limiting layer, or resistive layer, are configured to lower the current flow through the variable resistance layer during the logic state programming steps (i.e., “set” and “reset” steps) by adding a fixed series resistance in the formed resistive switching memory element found in the nonvolatile memory device.

Abstract: Barrier layers, barrier stacks, and seed layers for small-scale interconnects (e.g., copper) are combinatorially screened using test structures sputtered or co-sputtered through apertures of varying size. Various characteristics (e.g., resistivity, crystalline morphology, surface roughness) related to conductivity, diffusion blocking, and adhesion are measured before and/or after annealing and compared to arrive at materials and process parameters for low diffusion with high conductivity through the interconnect. Example results show that some formulations of tantalum-titanium barriers may replace thicker tantalum/tantalum-nitride stacks, in some cases with a Cu—Mn seed layer between the Ta—Ti and copper.

Abstract: An amorphous silicon (a-Si) dielectric for superconducting electronics is fabricated with reduced loss tangent by fluorine passivation throughout the bulk of the layer. Complete layers or thinner sub-layers of a-Si are formed by physical vapor deposition at low temperatures (<350 C, e.g. ˜200 C) to prevent reaction with superconducting materials, then exposed to fluorine. The fluorine may be a component of a gas or plasma, or it may be a component of an interface layer. The fluorine is driven into the a-Si by heat (e.g., <350 C) or impact to passivate defects such as dangling bonds.

Abstract: A gradient in the composition of at least one of the elements of a metal-based semiconductor layer is introduced as a function of depth through the layer. The gradient(s) influence the current density response of the device at different gate voltages. In some embodiments, the composition of an element (e.g. Ga) is greater at the interface between the metal-based semiconductor layer and the source/drain layers. The shape of the gradient profile is one of linear, stepped, parabolic, exponential, and the like.

Abstract: A method for making low emissivity panels, comprising forming a patterned layer on a transparent substrate. The patterned layers can offer different color schemes or different decorative appearance styles for the coated panels, or can offer gradable thermal efficiency through the patterned layers.

Abstract: Embodiments of the invention include a method of forming a nonvolatile memory device that contains a resistive switching memory element with improved device switching performance and lifetime, due to the addition of a current limiting component. In one embodiment, the current limiting component comprises a resistive material configured to improve the switching performance and lifetime of the resistive switching memory element. The electrical properties of the current limiting layer are configured to lower the current flow through the variable resistance layer during the logic state programming steps by adding a fixed series resistance in the resistive switching memory element found in the nonvolatile memory device. In one embodiment, the current limiting component comprises a tunnel oxide layer that is a current limiting material and an oxygen barrier layer that is an oxygen deficient material disposed within a resistive switching memory element in a nonvolatile resistive switching memory device.

Abstract: A transparent dielectric composition comprising tin, oxygen and one of aluminum or magnesium with preferably higher than 15% by weight of aluminum or magnesium offers improved thermal stability over tin oxide with respect to appearance and optical properties under high temperature processes. For example, upon a heat treatment at temperatures higher than 500 C, changes in color and index of refraction of the present transparent dielectric composition are noticeably less than those of tin oxide films of comparable thickness. The transparent dielectric composition can be used in high transmittance, low emissivity coated panels, providing thermal stability so that there are no significant changes in the coating optical and structural properties, such as visible transmission, IR reflectance, microscopic morphological properties, color appearance, and haze characteristics, of the as-coated and heated treated products.

Abstract: Metal oxide tunnel barrier layers for superconducting tunnel junctions are formed by atomic layer deposition. Both precursors include a metal (which may be the same metal or may be different). The first precursor is a metal alkoxide with oxygen bonded to the metal, and the second precursor is an oxygen-free metal precursor with an alkyl-reactive ligand such as a halogen or methyl group. The alkyl-reactive ligand reacts with the alkyl group of the alkoxide, forming a detached by-product and leaving a metal oxide monolayer. The temperature is selected to promote the reaction without causing the metal alkoxide to self-decompose. The oxygen in the alkoxide precursor is bonded to a metal before entering the chamber and remains bonded throughout the reaction that forms the monolayer. Therefore, the oxygen used in this process has no opportunity to oxidize the underlying superconducting electrode.

Abstract: Low emissivity panels can include a protection layer of silicon nitride on a layer of ZnO on a layer of Zn2SnOx. The low emissivity panels can also include NiNbTiOx as a barrier layer. The low emissivity panels have high light to solar gain, color neutral, together with similar observable color and light transmission before and after a heat treatment process.

Abstract: A method for forming a capacitor stack includes forming a first bottom electrode layer including a conductive metal nitride material. A second bottom electrode layer is formed above the first bottom electrode layer. The second bottom electrode layer includes a conductive metal oxide material, wherein the crystal structure of the conductive metal oxide material promotes a desired high-k crystal phase of a subsequently deposited dielectric layer. A dielectric layer is formed above the second bottom electrode layer. Optionally, an oxygen-rich metal oxide layer is formed above the dielectric layer. Optionally, a third top electrode layer is formed above the oxygen-rich metal oxide layer. The third top electrode layer includes a conductive metal oxide material. A fourth top electrode layer is formed above the third top electrode layer. The fourth top electrode layer includes a conductive metal nitride material.

Abstract: A resistor array for multi-bit data storage without the need to increase the size of a memory chip or scale down the feature size of a memory cell contained within the memory chip is provided. The resistor array incorporates a number of discrete resistive elements to be selectively connected, in different series combinations, to at least one memory cell or memory device. In one configuration, by connecting each memory cell or device with at least one resistor array, a resistive switching layer found in the resistive switching memory element of the connected memory device is capable of being at multiple resistance states for storing multiple bits of digital information. During device programming operations, when a desired series combination of the resistive elements within the resistor array is selected, the resistive switching layer in the connected memory device can be in a desired resistance state.

Abstract: Non-volatile resistive-switching memories are described, including a memory element having a first electrode, a second electrode, a metal oxide between the first electrode and the second electrode. The metal oxide switches using bulk-mediated switching, has a bandgap greater than 4 electron volts (eV), has a set voltage for a set operation of at least one volt per one hundred angstroms of a thickness of the metal oxide, and has a leakage current density less than 40 amps per square centimeter (A/cm2) measured at 0.5 volts (V) per twenty angstroms of the thickness of the metal oxide.

Abstract: Designs and programming schemes can be used to form memory arrays having low power, high density and good data retention. High resistance interconnect lines can be used to partition the memory array can be partitioned into areas of high data retention and areas of low data retention. Variable gate voltages can be used in control transistors to store memory values having different data retention characteristics.

Abstract: In a thin-film resistor stack (e.g. A ReRAM embedded resistor), a metallic barrier layer 1-5 nm thick protects an underlying or overlying ternary metal nitride layer from unwanted oxidation while having negligible effect on the resistance or height of the stack. For devices subjected to temperatures over 650 C after forming the stack, the metallic barrier layer may be iridium or ruthenium. For devices with temperatures kept below 650 C after forming the stack, the metallic barrier layer may be Al. The metallic barrier layer(s) and the ternary nitride layer may be formed in situ, for example by sputtering or atomic layer deposition.

Abstract: Provided are resistive random access memory (ReRAM) cells having switching layers that include hafnium, aluminum, oxygen, and nitrogen. The composition of such layers is designed to achieve desirable performance characteristics, such as low current leakage as well as low and consistent switching currents. In some embodiments, the concentration of nitrogen in a switching layer is between about 1 and 20 atomic percent or, more specifically, between about 2 and 5 atomic percent. Addition of nitrogen helps to control concentration and distribution of defects in the switching layer. Also, nitrogen as well as a combination of two metals helps with maintaining this layer in an amorphous state. Excessive amounts of nitrogen reduce defects in the layer such that switching characteristics may be completely lost. The switching layer may be deposited using various techniques, such as sputtering or atomic layer deposition (ALD).

Abstract: Methods for sealing a porous dielectric are presented including: receiving a substrate, the substrate including the porous dielectric; exposing the substrate to an organosilane, where the organosilane includes a hydrolysable group for facilitating attachment with the porous dielectric, and where the organosilane does not include an alkyl group; and forming a layer as a result of the exposing to seal the porous dielectric. In some embodiments, methods are presented where the organosilane includes: alkynyl groups, aryl groups, flouroalkyl groups, heteroarlyl groups, alcohol groups, thiol groups, amine groups, thiocarbamate groups, ester groups, ether groups, sulfide groups, and nitrile groups. In some embodiments, method further include: removing contamination from the porous dielectric and a conductive region of the substrate prior to the exposing; and removing contamination from the conductive region after the forming.

Abstract: Provided are resistive random access memory (ReRAM) cells and methods of fabricating thereof. The ReRAM cells may include a first layer operable as a bottom electrode and a second layer operable to switch between a first resistive state and a second resistive state. The ReRAM cells may include a third layer that includes a material having a lower breakdown voltage than the second layer and further includes a conductive path created by electrical breakdown. The third layer may include any of tantalum oxide, titanium oxide, and zirconium oxide. Moreover, the third layer may include a binary nitride or a ternary nitride. The binary nitrides may include any of tantalum, titanium, tungsten, and molybdenum. The ternary nitrides may include silicon or aluminum and any of tantalum, titanium, tungsten, and molybdenum. The ReRAM cells may further include a fourth layer operable as a top electrode.

Abstract: Provided are resistive random access memory (ReRAM) cells and methods of fabricating thereof. A stack including a defect source layer, a defect blocking layer, and a defect acceptor layer disposed between the defect source layer and the defect blocking layer may be subjected to annealing. During the annealing, defects are transferred in a controllable manner from the defect source layer to the defect acceptor layer. At the same time, the defects are not transferred into the defect blocking layer thereby creating a lowest concentration zone within the defect acceptor layer. This zone is responsible for resistive switching. The precise control over the size of the zone and the defect concentration within the zone allows substantially improvement of resistive switching characteristics of the ReRAM cell. In some embodiments, the defect source layer includes aluminum oxynitride, the defect blocking layer includes titanium nitride, and the defect acceptor layer includes aluminum oxide.