Patents Assigned to International Rectifier Corporation
  • Patent number: 9171784
    Abstract: A dual power converter package is disclosed. The package includes a leadframe having a first control FET paddle configured to support a drain of a first control FET, and a second control FET paddle configured to support a drain of a second control PET. The leadframe further includes a sync FET paddle configured to support a source of a first sync FET and a source of a second sync FET, and a first plurality of contacts configured to receive control signals for each of the control PETS and each of the sync FETs from a driver integrated circuit (IC) external to the leadframe. The leadframe may additionally include first and second switched nodes, configured for electrical connection to the first control FET and the first sync FET via a first clip, and to the second control PET and the second sync PET via a second clip, respectively.
    Type: Grant
    Filed: February 5, 2013
    Date of Patent: October 27, 2015
    Assignee: International Rectifier Corporation
    Inventors: Eung San Cho, Dan Clavette
  • Patent number: 9171743
    Abstract: According to example configurations herein, a leadframe includes a first conductive strip, a second conductive strip, and a third conductive strip disposed substantially adjacent and substantially parallel to each other. A semiconductor chip substrate includes a first array of switch circuits disposed adjacent and parallel to a second array of switch circuits. Source nodes in switch circuits of the first array are disposed substantially adjacent and substantially parallel to source nodes in switch circuits of the second array. When the semiconductor chip and the leadframe device are combined to form a circuit package, a connectivity interface between the semiconductor chip and conductive strips in the circuit package couples each of the source nodes in switch circuits of the first array and each of the multiple source nodes in switch circuits of the second array to a common conductive strip in the leadframe device.
    Type: Grant
    Filed: October 4, 2013
    Date of Patent: October 27, 2015
    Assignee: International Rectifier Corporation
    Inventors: Donald J. Desbiens, Gary D. Polhemus, Robert T. Carroll
  • Patent number: 9172306
    Abstract: A driver circuitry includes a capacitor, a first switch, and a second switch. The capacitor includes a first node and a second node. The first switch is electrically coupled to the first node of the capacitor. The second switch is electrically coupled to the second node of the capacitor. Additionally, the second node of the capacitor and the second switch are electrically coupled to an output pin of the driver circuitry operable to drive an external switch. As discussed herein, settings of the first switch and the second switch control a voltage outputted from the output pin and charging of the capacitor.
    Type: Grant
    Filed: March 5, 2014
    Date of Patent: October 27, 2015
    Assignee: International Rectifier Corporation
    Inventors: Danny Clavette, Xingsheng Zhou
  • Patent number: 9159679
    Abstract: According to one disclosed embodiment, a semiconductor package for integrated passives and a semiconductor device comprises a high permeability structure formed over a surface of the semiconductor package and surrounding a contact body of the semiconductor package, the contact body being connected to an output of the semiconductor device. The contact body can be, for example, a solder bump. The high permeability structure causes a substantial increase in inductance of the contact body so as to form an increased inductance inductor coupled to the output of the semiconductor device. In one embodiment, the semiconductor package further comprises a blanket insulator formed over the high permeability structure, and a capacitor stack formed over the blanket insulator. In one embodiment, the semiconductor device comprises a group III-V power semiconductor device.
    Type: Grant
    Filed: September 3, 2009
    Date of Patent: October 13, 2015
    Assignee: International Rectifier Corporation
    Inventor: Michael A. Briere
  • Patent number: 9159703
    Abstract: In one implementation, a semiconductor package includes a control conductive carrier having a die side and an opposite input/output (I/O) side connecting the semiconductor package to a mounting surface. The semiconductor package also includes a control FET of a power converter switching stage attached to the die side of the control conductive carrier, and a driver integrated circuit (IC) for driving the control FET. The driver IC is situated above the control FET and is electrically coupled to the control FET by at least one conductive buildup layer formed over the control conductive carrier.
    Type: Grant
    Filed: September 10, 2013
    Date of Patent: October 13, 2015
    Assignee: International Rectifier Corporation
    Inventors: Eung San Cho, Andrew N. Sawle, Mark Pavier, Daniel Cutler
  • Patent number: 9157169
    Abstract: A method for fabricating a III-nitride semiconductor body that includes high temperature and low temperature growth steps.
    Type: Grant
    Filed: September 13, 2006
    Date of Patent: October 13, 2015
    Assignee: International Rectifier Corporation
    Inventors: Paul Bridger, Robert Beach
  • Patent number: 9147644
    Abstract: According to one exemplary embodiment, a semiconductor package includes a substrate having lower and upper surfaces. The semiconductor package further includes at least one passive component coupled to first and second conductive pads on the upper surface of the substrate. The semiconductor package further includes at least one semiconductor device coupled to a first conductive pad on the lower surface of the substrate. The at least one semiconductor device has a first electrode for electrical and mechanical connection to a conductive pad external to the semiconductor package. The at least one semiconductor device can have a second electrode electrically and mechanically coupled to the first conductive pad on the lower surface of the substrate.
    Type: Grant
    Filed: June 5, 2009
    Date of Patent: September 29, 2015
    Assignee: International Rectifier Corporation
    Inventor: Martin Standing
  • Patent number: 9142503
    Abstract: Some exemplary embodiments of high voltage cascoded III-nitride semiconductor package utilizing clips on a package support surface have been disclosed. One exemplary embodiment comprises a III-nitride transistor attached to a package support surface and having an anode of a diode stacked over a source of the III-nitride transistor, a first conductive clip coupled to a gate of the III-nitride transistor and the anode of the diode, and a second conductive clip coupled to a drain of the III-nitride transistor. The conductive clips are connected to the package support surface and expose respective flat portions that are surface mountable. In this manner, reduced package footprint, improved surge current capability, and higher performance may be achieved compared to conventional wire bonded packages. Furthermore, since a low cost printed circuit board (PCB) may be utilized for the package support surface, expensive leadless fabrication processes may be avoided for cost effective manufacturing.
    Type: Grant
    Filed: July 16, 2014
    Date of Patent: September 22, 2015
    Assignee: International Rectifier Corporation
    Inventors: Chuan Cheah, Dae Keun Park
  • Patent number: 9142637
    Abstract: III-nitride materials are used to form isolation structures in high voltage ICs to isolate low voltage and high voltage functions on a monolithic power IC. Critical performance parameters are improved using III-nitride materials, due to the improved breakdown performance and thermal performance available in III-nitride semiconductor materials. An isolation structure may include a dielectric layer that is epitaxially grown using a III-nitride material to provide a simplified manufacturing process. The process permits the use of planar manufacturing technology to avoid additional manufacturing costs. High voltage power ICs have improved performance in a smaller package in comparison to corresponding silicon structures.
    Type: Grant
    Filed: February 15, 2011
    Date of Patent: September 22, 2015
    Assignee: International Rectifier Corporation
    Inventors: Robert Beach, Paul Bridger
  • Patent number: 9129890
    Abstract: There are disclosed herein various implementations of a semiconductor structure and method. The semiconductor structure comprises a substrate, a transition body over the substrate, and a group III-V intermediate body having a bottom surface over the transition body. The semiconductor structure also includes a group III-V device layer over a top surface of the group III-V intermediate body. The group III-V intermediate body has a continuously reduced impurity concentration wherein a higher impurity concentration at the bottom surface is continuously reduced to a lower impurity concentration at the top surface.
    Type: Grant
    Filed: July 31, 2014
    Date of Patent: September 8, 2015
    Assignee: International Rectifier Corporation
    Inventor: Michael A. Briere
  • Patent number: 9118126
    Abstract: According to one disclosed embodiment, a power semiconductor package includes an insulated-gate bipolar transistor (IGBT) residing on a package substrate, where the IGBT includes a plurality of solderable front metal (SFM) coated emitter segments situated atop the IGBT and connected to an emitter of the IGBT. The power semiconductor package also includes a conductive clip coupling the plurality of SFM coated emitter segments to an emitter pad on the package substrate. Additionally, the power semiconductor package includes a gate pad on the package substrate coupled to a gate of the IGBT, a collector pad on the package substrate situated under the IGBT and coupled to a collector of the IGBT, and an emitter terminal, a collector terminal and a gate terminal of the package substrate that are routed to the emitter pad, collector pad, and gate pad, respectively.
    Type: Grant
    Filed: January 11, 2013
    Date of Patent: August 25, 2015
    Assignee: International Rectifier Corporation
    Inventor: Hsueh-Rong Chang
  • Patent number: 9117671
    Abstract: A method of fabricating a III-nitride power semiconductor device that includes growing a transition layer over a substrate using at least two distinct and different growth methods.
    Type: Grant
    Filed: October 15, 2014
    Date of Patent: August 25, 2015
    Assignee: International Rectifier Corporation
    Inventors: Robert Beach, Michael A. Briere, Paul Bridger
  • Patent number: 9112009
    Abstract: A III-Nitride device has a back-gate disposed in a trench and under and in close proximity to the 2 DEG layer and in lateral alignment with the main gate of the device. A laterally disposed trench is also disposed in a trench and under and in close proximity to the drift region between the gate and drain electrodes of the device. The back-gate is connected to the main gate and the field plate is connected to the source electrode. The back-gate can consist of a highly conductive silicon substrate.
    Type: Grant
    Filed: September 16, 2008
    Date of Patent: August 18, 2015
    Assignee: International Rectifier Corporation
    Inventors: Alain Charles, Hamid Tony Bahramian
  • Patent number: 9111921
    Abstract: In one implementation, a semiconductor package includes a control conductive carrier having a die side and an opposite input/output (I/O) side connecting the semiconductor package to a mounting surface. The semiconductor package also includes a control FET of a power converter switching stage having a control drain attached to the die side of the control conductive carrier. The control conductive carrier is configured to sink heat produced by the control FET into the mounting surface. The semiconductor package includes a sync conductive carrier having another die side and another opposite I/O side connecting the semiconductor package to the mounting surface, and a sync FET of the power converter switching stage having a sync source attached to the die side of the sync conductive carrier.
    Type: Grant
    Filed: September 10, 2013
    Date of Patent: August 18, 2015
    Assignee: International Rectifier Corporation
    Inventors: Eung San Cho, Andrew N. Sawle, Mark Pavier, Daniel Cutler
  • Patent number: 9111776
    Abstract: In one implementation, a power semiconductor package includes a non-contiguous, multi-section conductive carrier. A control transistor with a control transistor terminal is coupled to a first section of the multi-section conductive carrier, while a sync transistor with a sync transistor terminal is coupled to a second section of the multi-section conductive carrier. The first and second sections of the multi-section conductive carrier sink heat generated by the control and sync transistors. The first and second sections of the multi-section conductive carrier are electrically connected only through a mounting surface attached to the power semiconductor package. Another implementation of the power semiconductor package includes a driver IC coupled to a third section of the multi-section conductive carrier. A method for fabricating the power semiconductor package is also disclosed.
    Type: Grant
    Filed: September 17, 2014
    Date of Patent: August 18, 2015
    Assignee: International Rectifier Corporation
    Inventor: Eung San Cho
  • Patent number: 9102242
    Abstract: The power switches of an inverter are mechanically integrated with an electric motor of a vehicle and are mounted on the end plate of the motor and employ short connections between the motor a-c terminals and the inverter a-c output terminals. Bond wireless modules are employed. The electronic controls for the inverter are mounted on a main control board which is positioned remotely from the inverter and is not subject to the heat and EMI produced by the inverter.
    Type: Grant
    Filed: August 2, 2007
    Date of Patent: August 11, 2015
    Assignee: International Rectifier Corporation
    Inventor: Henning Hauenstein
  • Patent number: 9105619
    Abstract: A semiconductor package that includes a semiconductor die and a heat spreader thermally coupled to the semiconductor and disposed at least partially within the molded housing of the package.
    Type: Grant
    Filed: February 15, 2013
    Date of Patent: August 11, 2015
    Assignee: International Rectifier Corporation
    Inventors: Michael A. Briere, Chuan Cheah, Kunzhong Hu
  • Patent number: 9105566
    Abstract: According to one disclosed embodiment, a method for fabricating a monolithic integrated composite device comprises forming a group III-V semiconductor body over a group IV semiconductor substrate, forming a trench in the group III-V semiconductor body, and forming a group IV semiconductor body in the trench. The method also comprises fabricating at least one group IV semiconductor device in the group IV semiconductor body, and fabricating at least one group III-V semiconductor device in the group III-V semiconductor body. In one embodiment, the method further comprises planarizing an upper surface of the III-V semiconductor body and an upper surface of the group IV semiconductor body to render those respective upper surfaces substantially co-planar. In one embodiment, the method further comprises fabricating at least one passive device in a defective region of said group IV semiconductor body adjacent to a sidewall of the trench.
    Type: Grant
    Filed: August 16, 2013
    Date of Patent: August 11, 2015
    Assignee: International Rectifier Corporation
    Inventor: Michael A. Briere
  • Patent number: 9105703
    Abstract: Disclosed is a III-nitride heterojunction device that includes a conduction channel having a two dimensional electron gas formed at an interface between a first III-nitride material and a second III-nitride material. A modification including a contact insulator, for example, a gate insulator formed under a gate contact, is disposed over the conduction channel, wherein the contact insulator includes aluminum to alter formation of the two dimensional electron gas at the interface. The contact insulator can include AlSiN, or can be SiN doped with aluminum. The modification results in programming the threshold voltage of the III-nitride heterojunction device to, for example, make the device an enhancement mode device. The modification can further include a recess, an ion implanted region, a diffused region, an oxidation region, and/or a nitridation region. In one embodiment, the first III-nitride material comprises GaN and the second III-nitride material comprises AlGaN.
    Type: Grant
    Filed: February 4, 2011
    Date of Patent: August 11, 2015
    Assignee: International Rectifier Corporation
    Inventor: Michael A. Briere
  • Patent number: 9099382
    Abstract: According to one embodiment, a III-nitride transistor includes a conduction channel formed between first and second III-nitride bodies, the conduction channel including a two-dimensional electron gas. The transistor also includes at least one gate dielectric layer having a charge confined within to cause an interrupted region of the conduction channel and a gate electrode operable to restore the interrupted region of the conduction channel. The transistor can be an enhancement mode transistor. In one embodiment, the gate dielectric layer is a silicon nitride layer. In another embodiment, the at least one gate dielectric layer is a silicon oxide layer. The charge can be ion implanted into the at least one gate dielectric layer. The at least one gate dielectric layer can also be grown with the charge.
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: August 4, 2015
    Assignee: International Rectifier Corporation
    Inventor: Michael A. Briere