Patents Assigned to International Rectifier Corporation
  • Patent number: 9007043
    Abstract: According to example configurations herein, a controller receives a value indicative of a number of phases in a power supply to be activated for producing an output voltage to power a load. A resonant frequency of the power supply changes depending on the number of phases activated. According to one configuration, a controller utilizes the value to proportionally adjust at least one control parameter associated with the power supply in accordance with a change in the resonant frequency. In addition to modifying a parameter based on the number of activated phases and/or the resonant frequency of the power supply, the controller can also use the value of the input voltage as a basis to adjust at least one control parameter. Moreover, according to one example configuration, the controller digitally computes values for the at least one control parameter based on a number of phases to be activated.
    Type: Grant
    Filed: December 1, 2011
    Date of Patent: April 14, 2015
    Assignee: International Rectifier Corporation
    Inventor: Venkat Sreenivas
  • Patent number: 9006921
    Abstract: Disclosed herein is an energy storage system and related method. According to one embodiment, such a system comprises a power management system and a plurality of energy banks coupled to the power management system, wherein each of the plurality of energy banks is capable of being independently discharged through the power management system. The power management system is configured to select at least one of the plurality of energy banks to transfer energy between the energy storage system and a machine powered using the energy storage system. According to one embodiment, the method comprises determining an energy transfer requirement of the machine powered by the energy storage system, selecting at least one of the plurality of energy banks for responding to the energy transfer requirement, and transferring energy between the selected energy bank(s) and the machine according to the energy transfer requirement.
    Type: Grant
    Filed: July 29, 2011
    Date of Patent: April 14, 2015
    Assignee: International Rectifier Corporation
    Inventors: Emil Yuming Chao, Charles Chang, Oleg Khaykin
  • Patent number: 9000829
    Abstract: According to an exemplary implementation, an integrated circuit (IC) includes a logic circuit monolithically formed on the IC. The logic circuit is configured to generate modulation signals for controlling power switches of a power inverter. The logic circuit generates the modulation signals based on at least one input value. The IC further includes a voltage level shifter monolithically formed on the IC. The voltage level shifter is configured to shift the modulation signals to a voltage level suitable for driving the power switches of the power inverter. The logic circuit can be a digital logic circuit and the input value can be a digital input value. The IC can also include a sense circuit monolithically formed on the IC. The sense circuit is configured to generate the input value.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: April 7, 2015
    Assignee: International Rectifier Corporation
    Inventors: Marco Giandalia, Toshio Takahashi, Massimo Grasso
  • Patent number: 9000746
    Abstract: A power converter driver that is supplied with two different voltages.
    Type: Grant
    Filed: November 17, 2011
    Date of Patent: April 7, 2015
    Assignee: International Rectifier Corporation
    Inventors: Michael A. Briere, Jason Zhang, HamidTony Bahramian
  • Patent number: 9000512
    Abstract: An assembler receives a circuit device and a mass of conductive material such as a diode, metal material, etc. The assembler bonds a first facing of a circuit device to a substrate. Adjacent to the circuit device, the assembler bonds a first facing of the mass of conductive material to the substrate. The assembler applies an overmold layer of insulation material over the substrate adjacent the circuit device and the mass of conductive material. Subsequent to applying the overmold layer of insulation material, the assembler provides a conductive link between a second facing of the circuit device and a second facing of the mass of conductive material.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: April 7, 2015
    Assignee: International Rectifier Corporation
    Inventors: Florian Bieck, Robert J. Montgomery
  • Patent number: 9001518
    Abstract: According to an exemplary embodiment, a bondwireless power module residing on a top surface of a substrate includes at least one input power pad providing power to the module and at least one output current pad providing output current from the module. At least one press-fit input power clamp engages a top side of the at least one input power pad, and engages a bottom surface of the substrate. Also, at least one press-fit output current clamp engages a top side of the at least one output current pad, and engages the bottom surface of the substrate. The at least one press-fit input power clamp can include at least one top prong and at least one bottom prong. Furthermore, the at least one bottom prong can press the input power pad into the at least one top prong.
    Type: Grant
    Filed: April 26, 2011
    Date of Patent: April 7, 2015
    Assignee: International Rectifier Corporation
    Inventor: Henning M. Hauenstein
  • Patent number: 9000486
    Abstract: A III-nitride heterojunction semiconductor device having a III-nitride heterojunction that includes a discontinuous two-dimensional electron gas under a gate thereof.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: April 7, 2015
    Assignee: International Rectifier Corporation
    Inventors: Paul Bridger, Robert Beach
  • Patent number: 8987883
    Abstract: One exemplary disclosed embodiment comprises a high power semiconductor package configured as a buck converter having a control transistor and a sync transistor disposed on a common leadframe pad, a driver integrated circuit (IC) for driving the control and sync transistors, and conductive clips electrically coupling the top surfaces of the transistors to substrate pads such as leadframe pads. In this manner, the leadframe and the conductive clips provide efficient grounding or current conduction by direct mechanical connection and large surface area conduction, thereby enabling a package with significantly reduced electrical resistance, form factor, complexity, and cost when compared to conventional packaging methods using wirebonds for transistor interconnections.
    Type: Grant
    Filed: February 27, 2014
    Date of Patent: March 24, 2015
    Assignee: International Rectifier Corporation
    Inventors: Eung San Cho, Chuan Cheah
  • Patent number: 8987051
    Abstract: One exemplary disclosed embodiment comprises a semiconductor package including an inside pad, a transistor, and a conductive clip coupled to the inside pad and a terminal of the transistor. A top surface of the conductive clip is substantially exposed at the top of the package, and a side surface of the conductive clip is exposed at a side of the package. By supporting the semiconductor package on an outside pad during the fabrication process and by removing the outside pad during singulation, the conductive clip may be kept substantially parallel and in alignment with the package substrate while optimizing the package form factor compared to conventional packages. The exposed top surface of the conductive clip may be further attached to a heat sink for enhanced thermal dissipation.
    Type: Grant
    Filed: August 17, 2013
    Date of Patent: March 24, 2015
    Assignee: International Rectifier Corporation
    Inventor: Eung San Cho
  • Patent number: 8987777
    Abstract: According to an exemplary embodiment, a stacked half-bridge power module includes a high side device having a high side power terminal coupled to a high side substrate and a low side device having a low side power terminal coupled to a low side substrate. The high side and low side devices are stacked on opposite sides of a common conductive interface. The common conductive interface electrically, mechanically, and thermally couples a high side output terminal of the high side device to a low side output terminal of the low side device. The high side device and the low side device can each include an insulated-gate bipolar transistor (IGBT) in parallel with a diode.
    Type: Grant
    Filed: July 21, 2011
    Date of Patent: March 24, 2015
    Assignee: International Rectifier Corporation
    Inventor: Henning M. Hauenstein
  • Patent number: 8987833
    Abstract: In one implementation, a stacked composite device comprises a group IV lateral transistor and a group III-V transistor stacked over the group IV lateral transistor. A drain of the group IV lateral transistor is in contact with a source of the group III-V transistor, a source of the group IV lateral transistor is coupled to a gate of the group III-V transistor to provide a composite source on a top side of the stacked composite device, and a drain of the group III-V transistor provides a composite drain on the top side of the stacked composite device. A gate of the group IV lateral transistor provides a composite gate on the top side of the stacked composite device, and a substrate of the group IV lateral transistor is on a bottom side of the stacked composite device.
    Type: Grant
    Filed: March 29, 2012
    Date of Patent: March 24, 2015
    Assignee: International Rectifier Corporation
    Inventors: Tim McDonald, Michael A. Briere
  • Patent number: 8987898
    Abstract: According to one embodiment, a semiconductor wafer comprises a plurality of solder bumps for providing device contacts formed over a functional region of the semiconductor wafer, and one or more support rings surrounding the functional region. The one or more support rings and the plurality of solder bumps are formed so as to have substantially matching heights. The presence of the one or more support rings causes the semiconductor wafer to have a substantially uniform thickness in the functional region after a thinning process is performed on the semiconductor wafer. A method for fabricating the semiconductor wafer comprises forming the plurality of solder bumps over the functional region, and forming the one or more support rings surrounding the functional region before performing the thinning process on the semiconductor wafer.
    Type: Grant
    Filed: June 6, 2011
    Date of Patent: March 24, 2015
    Assignee: International Rectifier Corporation
    Inventors: Rupert Burbidge, David Paul Jones, Amarjit Dhadda, Robert Montgomery
  • Patent number: 8988128
    Abstract: According to an exemplary implementation, a level shifter includes a low voltage circuit and a high voltage circuit. The low voltage circuit is configured to provide a differential signal to the high voltage circuit. The high voltage circuit is configured to receive the differential signal from the low voltage circuit so as to level shift the differential signal from a first ground of the low voltage circuit to a second ground of the high voltage circuit. The differential signal is provided by the low voltage circuit responsive to a feedback signal from the high voltage circuit. The feedback signal can indicate common mode noise in the level shifter. Furthermore, the low voltage circuit can be configured to refresh the differential signal responsive to the feedback signal.
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: March 24, 2015
    Assignee: International Rectifier Corporation
    Inventors: Min Fang, Massimo Grasso, Niraj Ranjan
  • Patent number: 8987784
    Abstract: In an exemplary implementation, a III-nitride semiconductor device includes a III-nitride heterojunction including a first III-nitride body situated over a second III-nitride body to form a two-dimensional electron gas. The III-nitride semiconductor device further includes a dielectric body situated over the III-nitride heterojunction and including a first dielectric layer of a first dielectric material and a second dielectric layer of a second dielectric material different than the first dielectric material. A gate well of a first width is defined by the first dielectric layer, and is of a second width defined by the second dielectric layer, where the second width is greater than the first width. The III-nitride semiconductor device further includes a gate arrangement situated in the gate well and including a gate electrode integrated with a field plate.
    Type: Grant
    Filed: November 15, 2013
    Date of Patent: March 24, 2015
    Assignee: International Rectifier Corporation
    Inventor: Michael A. Briere
  • Patent number: 8988133
    Abstract: There are disclosed herein various implementations of nested composite switches. In one implementation, a nested composite switch includes a normally ON primary transistor coupled to a composite switch. The composite switch includes a low voltage (LV) transistor cascoded with an intermediate transistor having a breakdown voltage greater than the LV transistor and less than the normally ON primary transistor. In one implementation, the normally on primary transistor may be a group III-V transistor and the LV transistor may be an LV group IV transistor.
    Type: Grant
    Filed: July 5, 2012
    Date of Patent: March 24, 2015
    Assignee: International Rectifier Corporation
    Inventor: Michael A. Briere
  • Patent number: 8981380
    Abstract: Disclosed is a monolithically integrated silicon and group III-V device that includes a group III-V transistor formed in a III-V semiconductor body disposed over a silicon substrate. At least one via extends through the III-V semiconductor body to couple at least one terminal of the group III-V transistor to a silicon device formed in the silicon substrate. The silicon device can be a Schottky diode, and the group III-V transistor can be a GaN HEMT. In one embodiment an anode of the Schottky diode is formed in the silicon substrate. In another embodiment, the anode of the Schottky diode is formed in a lightly doped epitaxial silicon layer atop the silicon substrate. In one embodiment a parallel combination of the Schottky diode and the group III-V transistor is formed, while in another embodiment is series combination is formed.
    Type: Grant
    Filed: December 3, 2010
    Date of Patent: March 17, 2015
    Assignee: International Rectifier Corporation
    Inventor: Michael A. Briere
  • Patent number: 8969881
    Abstract: There are disclosed herein various implementations of a transistor having a segmented gate region. Such a transistor may include at least one segmentation dielectric segment and two or more gate dielectric segments. The segmentation dielectric segment or segments are thicker than the gate dielectric segments, and is/are situated between the gate dielectric segments. The segmentation dielectric segment or segments cause an increase in the effective gate length so as to improve resistance to punch-through breakdown between a drain electrode and a source electrode of the transistor when the transistor is off.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: March 3, 2015
    Assignee: International Rectifier Corporation
    Inventors: Michael A. Briere, Naresh Thapar
  • Patent number: 8970021
    Abstract: One exemplary disclosed embodiment comprises a semiconductor package including an inside pad, a transistor, and a conductive clip coupled to the inside pad and a terminal of the transistor. A top surface of the conductive clip is substantially exposed at the top of the package, and a side surface of the conductive clip is exposed at a side of the package. By supporting the semiconductor package on an outside pad during the fabrication process and by removing the outside pad during singulation, the conductive clip may be kept substantially parallel and in alignment with the package substrate while optimizing the package form factor compared to conventional packages. The exposed top surface of the conductive clip may be further attached to a heat sink for enhanced thermal dissipation.
    Type: Grant
    Filed: September 6, 2013
    Date of Patent: March 3, 2015
    Assignee: International Rectifier Corporation
    Inventor: Eung San Cho
  • Patent number: 8963442
    Abstract: According to one exemplary embodiment, driver circuit coupled between an AC line and a load includes a first semiconductor switch interposed between a bus voltage and a resonant circuit and a second semiconductor switch interposed between the resonant circuit and a ground, where the resonant circuit drives the load. In the driver circuit, the bus voltage has a shape substantially corresponding to a shape of a rectified AC line voltage, thereby increasing a power factor of the driver circuit. The driver circuit can further include a full-bridge rectifier disposed between the resonant circuit and the load. The load can include at least one LED.
    Type: Grant
    Filed: November 4, 2009
    Date of Patent: February 24, 2015
    Assignee: International Rectifier Corporation
    Inventor: Thomas J. Ribarich
  • Patent number: 8963338
    Abstract: One exemplary disclosed embodiment comprises a two-terminal stacked-die package including a diode, such as a silicon diode, stacked atop a III-nitride transistor, such that a cathode of the diode resides on and is electrically coupled to a source of the III-nitride transistor. A first terminal of the package is coupled to a drain of the III-nitride transistor, and a second terminal of the package is coupled to an anode of the diode. In this manner, devices such as cascoded rectifiers may be packaged in a stacked-die form, resulting in reduced parasitic inductance and resistance, improved thermal dissipation, smaller form factor, and lower manufacturing cost compared to conventional packages.
    Type: Grant
    Filed: March 22, 2011
    Date of Patent: February 24, 2015
    Assignee: International Rectifier Corporation
    Inventors: Heny Lin, Jason Zhang, Alberto Guerra