Abstract: Some exemplary embodiments of a multi-chip semiconductor package utilizing a semiconductor substrate and related method for making such a semiconductor package have been disclosed. One exemplary embodiment comprises a first semiconductor device including, on a surface thereof, a first patterned dielectric layer, a conductive redistribution layer, a second patterned dielectric layer, and a second semiconductor device. The conductive redistribution layer connects to a first and a second patterned conductive attach material for connecting the first and second semiconductor devices to provide coplanar electrical connections for mounting on a printed circuit board. In one embodiment, the first semiconductor device is a diode having anode and cathode contacts on an upper surface thereof, and the second semiconductor device is an IGBT.

Abstract: The invention provides semiconductor materials including a gallium nitride material layer formed on a silicon substrate and methods to form the semiconductor materials. The semiconductor materials include a transition layer formed between the silicon substrate and the gallium nitride material layer. The transition layer is compositionally-graded to lower stresses in the gallium nitride material layer which can result from differences in thermal expansion rates between the gallium nitride material and the substrate. The lowering of stresses in the gallium nitride material layer reduces the tendency of cracks to form. Thus, the invention enables the production of semiconductor materials including gallium nitride material layers having few or no cracks. The semiconductor materials may be used in a number of microelectronic and optical applications.

Abstract: Some exemplary embodiments of a multi-chip module (MCM) power quad flat no-lead (PQFN) semiconductor package utilizing a leadframe for electrical interconnections have been disclosed. One exemplary embodiment comprises a PQFN semiconductor package comprising a leadframe, a driver integrated circuit (IC) coupled to the leadframe, a plurality of vertical conduction power devices coupled to the leadframe, and a plurality of wirebonds providing electrical interconnects, including at least one wirebond from a top surface electrode of one of the plurality of vertical conduction power devices to a portion of the leadframe, wherein the portion of the leadframe is electrically connected to a bottom surface electrode of another of the plurality of vertical conduction power devices. In this manner, efficient multi-chip circuit interconnections can be provided in a PQFN package using low cost leadframes.

Abstract: A DC-DC voltage converter having a switching stage including high- and low-side switches connected in series at a switched node across a DC voltage bus; a control circuit; and a feedback loop connected between an output of the switching stage and an input of the control circuit, the control circuit having a clock signal input and including an error processing circuit coupled to the input for detecting an output of the feedback loop, the control circuit turning OFF the low-side switch and turning ON the high-side switch when the clock signal is detected. The control circuit operates in a cycle-by-cycle operation generating PWM modulation synchronous to the external clock source.

Abstract: According to example configurations herein, a leadframe includes a first conductive strip, a second conductive strip, and a third conductive strip disposed substantially adjacent and substantially parallel to each other. A semiconductor chip substrate includes a first array of switch circuits disposed adjacent and parallel to a second array of switch circuits. Source nodes in switch circuits of the first array are disposed substantially adjacent and substantially parallel to source nodes in switch circuits of the second array. When the semiconductor chip and the leadframe device are combined to form a circuit package, a connectivity interface between the semiconductor chip and conductive strips in the circuit package couples each of the source nodes in switch circuits of the first array and each of the multiple source nodes in switch circuits of the second array to a common conductive strip in the leadframe device.

Abstract: According to one exemplary embodiment, a group III-V semiconductor device includes at least one transition layer situated over a substrate. The group III-V semiconductor device further includes a first strain-relieving interlayer situated over the at least one transition layer and a second strain-relieving interlayer situated over the first strain-relieving interlayer. The group III-V semiconductor device further includes a first group III-V semiconductor body situated over the second strain-relieving interlayer. The first and second strain-relieving interlayers comprise different semiconductor materials so as to reduce a strain in the first group III-V semiconductor body. The second strain-relieving interlayer can be substantially thinner than the first strain-relieving interlayer.

Abstract: Some exemplary embodiments of an advanced direct contact leadless package and related structure and method, especially suitable for packaging high current semiconductor devices, have been disclosed. One exemplary structure comprises a mold compound enclosing a first contact lead frame portion, a paddle portion, and an extended contact lead frame portion held together by a mold compound. A first semiconductor device is attached on top of the lead frame portions as a flip chip, while a second semiconductor device is attached to a bottom side of said paddle portion and is in electrical contact with said the first semiconductor device. The extended contact lead frame portion is in direct electrical contact with the second semiconductor device without using a bond wire. Alternative exemplary embodiments may include additional extended lead frame portions, paddle portions, and semiconductor devices in various configurations.

Abstract: Some exemplary embodiments of an advanced direct contact leadless package and related structure and method, especially suitable for packaging high current semiconductor devices, have been disclosed. One exemplary structure comprises a mold compound enclosing a first contact lead frame portion, a paddle portion, and an extended contact lead frame portion held together by a mold compound. A first semiconductor device is attached on top of the lead frame portions as a flip chip, while a second semiconductor device is attached to a bottom side of said paddle portion and is in electrical contact with said the first semiconductor device. The extended contact lead frame portion is in direct electrical contact with the second semiconductor device without using a bond wire. Alternative exemplary embodiments may include additional extended lead frame portions, paddle portions, and semiconductor devices in various configurations.

Abstract: A semiconductor device package is formed of DBC in which thinned MOSgated and/or diode die are soldered to the bottom of an etched depression in the upper conductive layer. A via in the insulation layer of the DBC is filled with a conductive material to form a resistive shunt. Plural packages may be formed in a DBC card and may be separated individually or in clusters. The individual packages are mounted in various arrays on a support DBC board and heat sink. Integrated circuits may be mounted on the assembly and connected to the die for control of the die conduction.

Abstract: In one implementation, a power converter with over-voltage protection includes a power switch coupled to a power supply through a tank circuit, and a control circuit coupled to a gate of the power switch. The control circuit is configured to turn the power switch OFF based on a current from the tank circuit, thereby providing the over-voltage protection to the power converter. In one implementation, the power converter is a class-E power converter. In one implementation, the control circuit is configured to sense the current from the tank circuit based on a voltage drop across a sense resistor coupled to the power switch.

Abstract: In one implementation, a diode providing a substantially oscillation free fast-recovery includes at least one anode diffusion formed at a front side of a semiconductor die, and a cathode layer formed at a back side of the semiconductor die. The diode also includes a drift region and a buffer layer situated between the drift region and the cathode layer to enable the substantially oscillation free fast-recovery by the diode. In one implementation, the buffer layer is N type doped using hydrogen as a dopant.

Abstract: There are disclosed herein various implementations of a method and a system enabling operation of a motor in reverse. Such a method includes applying a first drive signal to begin rotating the motor in a reverse direction, the first drive signal being applied for a predetermined period of time. The method also includes using a position sensor signal for the motor to control motor drive in the reverse direction when the motor reaches a predetermined reverse speed, and operating the motor in the reverse direction.

Abstract: A power semiconductor device that includes a buried source electrode disposed at the bottom of a trench below a respective gate electrode, and a source connector including a finger electrically connecting the buried source to the source contact of the device, and a process for fabricating the device.

Abstract: A semiconductor package that includes a semiconductor die and a heat spreader thermally coupled to the semiconductor and disposed at least partially within the molded housing of the package.

Abstract: According to an exemplary implementation, an integrated circuit (IC) includes a logic circuit monolithically formed on the IC. The logic circuit is configured to generate modulation signals for controlling power switches of a power inverter. The logic circuit generates the modulation signals based on at least one input value. The IC further includes a voltage level shifter monolithically formed on the IC. The voltage level shifter is configured to shift the modulation signals to a voltage level suitable for driving the power switches of the power inverter. The logic circuit can be a digital logic circuit and the input value can be a digital input value. The IC can also include a sense circuit monolithically formed on the IC. The sense circuit is configured to generate the input value.

Abstract: According to one disclosed embodiment, a monolithic vertically integrated composite device comprises a double sided semiconductor substrate having first and second sides, a group IV semiconductor layer formed over the first side and comprising at least one group IV semiconductor device, and a group III-V semiconductor body formed over the second side and comprising at least one group III-V semiconductor device electrically coupled to the at least one group IV semiconductor device. The composite device may further comprise a substrate via and/or a through-wafer via providing electric coupling. In one embodiment, the group IV semiconductor layer may comprise an epitaxial silicon layer, and the at least one group IV semiconductor device may be a combined FET and Schottky diode (FETKY) fabricated on the epitaxial silicon layer. In one embodiment, the at least one group III-V semiconductor device may be a III-nitride high electron mobility transistor (HEMT).

Abstract: A method for fabrication of a III-nitride film over a silicon wafer that includes forming control joints to allow for overall stress relief in the III-nitride film during the growth thereof.

Abstract: A power supply circuit can be configured to include a first circuit and a second circuit. Each circuit can be substantially identical to each other but provide different functionality depending on how they are configured. For example, each of the first circuit and second circuit can be chips having substantially the same pin layout and internal circuitry. However, the functionality provided by the circuits varies depending on whether a respective circuit is configured as a master or slave. The first circuit is configured as the master and generates multiple phase control signals. The first circuit uses a portion of the multiple phase control signals to control a first set of phases. The first circuit transmits a second portion of the multiple phase control signals to the second circuit configured as a slave. The second circuit is configured to receive and use the second portion of control signals to control a second set of phases.

Abstract: To reduce gate-drive losses caused by high switching frequency operation, embodiments herein include a novel resonant gate driver circuit for driving switches. This gate drive circuit can include a simple two-half-bridge structure. A coupling inductor of the resonant gate driver circuit can provide energy circulation between gates of high and low side switches and also works as a voltage-boost transformer. According to one configuration, the resonant gate driver circuit can be extended to drive two MOSFETs with a common ground. Both theoretical and simulation results for the new resonant gate driver circuit illustrate increased efficiency via lower switching losses.

Abstract: There are disclosed herein various implementations of a power converter having an advanced control integrated circuit (IC). The power converter includes the control IC and a power switch. The control IC includes a driving stage for driving the power switch, and a sensing stage coupled to the driving stage. The sensing stage is configured to produce a control signal for the driving stage based on an output current of the power converter sensed at a high side bus of the power converter.