Abstract: A semiconductor structure comprises a top metal layer, a bond pad formed on the top metal layer, a conductor formed below the top metal layer, and an insulation layer separating the conductor from the top metal layer. The top metal layer includes a sub-layer of relatively stiff material compared to the remaining portion of the top metal layer. The sub-layer of relatively stiff material is configured to distribute stresses over the insulation layer to reduce cracking in the insulation layer.

Abstract: In a switch mode power supply, a circuit and method for switching between an internal clock and an external synchronization clock when a stable external clock has been detected, and for switching back to operating the power supply using said internal clock when a predetermined number of sequential external clock pulses exceed a predetermined switching period dropout threshold or are otherwise missing. In one embodiment, a power system comprises a plurality of power supplies connected in parallel to a common load and where each power supply is synchronized to the external clock when a stable external clock has been detected by each.

Abstract: An embodiment of a power supply includes an input node that receives an input voltage, an output node on which a regulated output voltage is provided, an odd number of magnetically coupled phase paths each coupled between the input and output nodes, and a first magnetically uncoupled phase path coupled between the input and output nodes. Such a power supply can improve its efficiency by activating different combinations of the coupled and uncoupled phase paths depending on the load conditions. For example, the power supply may activate only an uncoupled phase path during light-load conditions, may activate only coupled phase paths during moderate-load conditions, and may activate both coupled and uncoupled phase paths during heavy-load conditions and during a step-up load transient.

Abstract: A converter system including a cascade boost converter and inverting buck converter and controller for converting a rectified AC voltage to a DC output current. The system uses inductors and is configured to use a common reference voltage. The controller is configured to control switching of the converters in an independent manner to decouple operation from each other. For example, control pulses for the boost converter may be wider than pulses for the buck converter. The controller may control the boost converter based on constant on-time control and may control the inverting buck converter based on peak current control. The rectified AC voltage may be an AC conductive angle modulated voltage, where the controller may inhibit switching of the inverted buck converter at a dimming frequency having a duty cycle based on a phase angle of the AC conductive angle modulated voltage.

Abstract: A circuit, device, and method for controlling a buck-boost circuit includes a bootstrap capacitor voltage regulator circuit and a comparator circuit. The bootstrap capacitor voltage regulator circuit is electrically coupled to a buck-mode bootstrap capacitor of the buck-boost converter and to a boost-mode bootstrap capacitor of the buck-boost converter. The comparator circuit is configured to control the bootstrap capacitor voltage regulator circuit to maintain a voltage of the bootstrap capacitors above a reference threshold voltage by transferring an amount energy from one of the bootstrap capacitors to the other bootstrap capacitors based on the particular mode of operation of the buck-boost converter.

Abstract: A method for manufacturing an optoelectronic apparatus includes attaching bottom surfaces of first and second packaged optoelectronic semiconductor devices (POSDs) to a carrier substrate (e.g., a tape) so that there is a space between the first and second POSDs. An opaque molding compound is molded around portions of the first and second POSDs attached to the carrier substrate, so that peripheral surfaces of the first POSD and the second POSD are surrounded by the opaque molding compound, the space between the first and second POSDs is filled with the opaque molding compound, and the first and second POSDs are attached to one another by the opaque molding compound. The carrier substrate is thereafter removed so that electrical contacts on the bottom surfaces of the first and second POSDs are exposed. A window for each of the POSDs is formed during the molding process or thereafter.

Abstract: A spread spectrum clock signal generator and an accompanying method provide a spread spectrum clock signal of a reduced electromagnetic interference. The spread spectrum clock signal generator includes (a) a state machine, which maintains a current state of the spread spectrum clock signal generator, receives as input value a next state of the spread spectrum clock signal generator and generates a clock phase selection signal based on the current and next states; (b) a random number generator for generating the next state; and (c) a waveform generation circuit for generating a spread spectrum clock signal based on the clock phase selection signal.

Abstract: A buck boost converter generates a regulated output voltage responsive to an input voltage and switching control signals. Switching control circuitry generates the switching control signals responsive to the regulated output voltage, a maximum duty cycle signal and a mode signal. Mode control circuitry generates the maximum duty cycle signal and the mode signal responsive to a buck PWM signal and a boost PWM signal, a first clock signal and a second clock signal phase shifted from the first clock signal by a fixed, programmable amount. A phase shifter generates the first clock signal and the second clock signal responsive to a reference voltage and a synchronization signal.

Abstract: INL values are determined for sub-segments of a DAC adapted to accept N bit digital input codes, and a first set of correction codes that can be used to reduce to a range of INL values (to improve linearity of the DAC) are determined and stored. Additionally, DNL values are determined for the sub-segments of the DAC, and a second set of correction codes that can be used to ensure that all values of DNL>?1 (to ensure that the DAC is monotonic) are determined and stored. This can include using one or more extra bits of resolution to remap at least some of the 2^N possible digital input codes (that can be accepted by the DAC) to more than 2^N possible digital output codes, to ensure that all values of DNL>?1. Such stored first and second sets are thereafter used when performing digital to analog conversions.

Abstract: A delay locked loop (DLL) includes a phase detector (PD), a lock assistor (LA), a control voltage generator, and a voltage controlled delay line (VCDL). The PD determines a phase difference between of a reference clock and a delayed version of the reference clock and produces a pair of phase detector output signals in dependence on the determined phase difference. The LA receives the pair of phase detector output signals and produces a pair of lock assist output signals by selectively swapping the phase detector output signals. The control voltage generator receives the pair of lock assist output signals and produces a control voltage signal in dependence on thereon. The VCDL receives the control voltage signal and the reference clock (or a buffered version thereof) and outputs the delayed version of the reference clock, with a delay through the VCDL being dependent on the received control voltage signal.

Abstract: A semiconductor package comprises a bond pad formed on a first semiconductor die, a surface of the bond pad exposed through an opening in a passivation layer on the first semiconductor die; a raised conductive area formed on top of a passivation layer on a second semiconductor die; and a bond wire having a first end coupled to the bond pad via a ball bond and a second end coupled directly to a surface of the raised conductive area via a stitch bond. The raised conductive area is comprised of a plurality of metal layers, each of the metal layers comprised of a respective material and having a respective thickness. The thickness and material of at least one of the plurality of metal layers is selected such that a hardness of the raised conductive area is at least as hard as a hardness of the bond wire.

Abstract: Exemplary embodiments provide a solar cell device, and method for forming the solar cell device by integrating a switch component into a solar cell element. The solar cell element can include a solar cell, a solar cell array and/or a solar cell panel. The integrated solar cell element can be used for a solar sensor, while the solar sensor can also use discrete switches for each solar cell area of the sensor. Exemplary embodiments also provide a connection system for the solar cell elements and a method for super-connecting the solar cell elements to provide a desired connection path or a desired power output through switch settings. The disclosed connection systems and methods can allow for by-passing underperforming solar cell elements from a plurality of solar cell elements. In embodiments, the solar cell element can be extended to include a battery or a capacitor.

Abstract: A time-interleaved analog to digital converter (TIADC) that uses a digital filter to remove sampling-frequency symmetries that might otherwise degrade error correction. In an embodiment, two Analog to Digital Converter (ADC) cores provide a set of two ADC outputs. Interleaving the digital signals output by the ADC cores forms a digital representation of the input signal. The ADC cores have an offset correction input, a gain correction input, or a sample time correction input. Prior to estimating one or more of these errors, the ADC core output signals are filtered, with the filtering depending upon expected aliasing characteristics of the input signal.

Abstract: A method of operating a regulator controller IC for performing intermittent diode braking for controlling a multiple phase voltage regulator. The method includes receiving at least one signal for detecting repetitive load transients, determining a rate of the repetitive load transients, generating diode braking control signals, each for applying diode braking to a corresponding one of multiple phases for at least one load transient when the repetitive load transients are below a first rate, and controlling the diode braking control signals to drop application of diode braking of at least one phase for at least one load transient when the repetitive load transients are at least the first rate. The method may include rotating the application of diode braking among the phases during successive applications of diode braking. The method may include dropping an increased number of phases for diode braking as the rate of repetitive load transients is increased.

Abstract: Provided herein are methods and systems that provide automatic compensation for frequency attenuation of a video signal transmitted over a cable. In accordance with an embodiment, a system includes an equalizer and a compensation controller. The equalizer receives a video signal that was transmitted over a cable, provides compensation for frequency attenuation that occurred during the transmission over the cable, and outputs a compensated video signal. The compensation controller automatically adjusts the compensation provided by the equalizer based on comparisons of one or more portions of the compensated video signal to one or more reference voltage levels. The compensating is selectively locked and reset in response to specific conditions being detected, e.g., a locking condition and a reset condition.

Abstract: A semiconductor device is provided and includes a semiconductor die, and a plurality of bond pads having exposed surfaces arranged in an alternating interleaved pattern on the semiconductor die. Each of the surfaces of the bond pads have a first bond placement area that overlaps with a second bond placement area, with the first bond placement area having a major axis that is orthogonal to a major axis of the second bond placement area. A connecting bond is located at an intersection of the major axes of the first bond placement area and the second bond placement area on one or more of the bond pads.

Abstract: An EMI reduction network for a converter, the converter including upper and lower power switches provided between an input voltage node and a reference node. An inductance is coupled between the input voltage node and the upper switch at a first node, a capacitance and an auxiliary power switch are coupled in series between the first and reference nodes, and a controller is provided to control switching. The controller switches the upper switch based on a PWM signal. The controller keeps the lower switch turned on until the phase node goes positive while the upper switch is on. The controller turns the auxiliary switch on after the lower power switch is turned off and turns the auxiliary switch off after the upper power switch is turned off. The lower and auxiliary switches may be zero voltage switched, and the upper switch may be zero current switched.

Abstract: A regulator controller which controls conversion of an input voltage to an output voltage, including a switching regulator, a low dropout (LDO) regulator, and a mode controller. The switching regulator develops a pulse control signal to regulate the output voltage when enabled. The LDO regulator also regulates the output voltage when enabled. The mode controller enables or disables the switching regulator and the LDO regulator based on a load condition. The switching regulator is enabled and the LDO regulator is disabled during normal operation. The LDO regulator is enabled when the low load condition is detected, such as a skipped pulse on the pulse control signal. The switching regulator is disabled when the pulse control signal reaches a minimum level. The LDO regulator is disabled and the switching regulator is re-enabled based on threshold conditions of the current output of the LDO regulator.

Abstract: A voltage converter includes an output circuit having a high side device and a low side device which can be formed on a single die (i.e. a “PowerDie”) and connected to each other through a semiconductor substrate. Both the high side device and the low side device can include lateral diffused metal oxide semiconductor (LDMOS) transistors. Because both output transistors include the same type of transistors, the two devices can be formed simultaneously, thereby reducing the number of photomasks over other voltage converter designs. The voltage converter can further include a controller circuit on a different die which can be electrically coupled to, and co-packaged with, the PowerDie.

Abstract: Light sensors including dielectric optical coatings to shape their spectral responses, and methods for fabricating such light sensors in a manner that accelerates lift-off processes and increases process margins, are described herein. In certain embodiments, a short duration soft bake is performed. Alternatively, or additionally, temperature cycling is performed. Alternatively, or additionally, photolithography is performed using a photomask that includes one or more dummy corners, dummy islands and/or dummy rings. Each of the aforementioned embodiments form and/or increase a number of micro-cracks in the dielectric optical coating not covering the photodetector sensor region, thereby enabling an accelerated lift-off process and an increased process margin. Alternatively, or additionally, a portion of the photomask can include chamfered corners so that the dielectric optical coating includes chamfered corners, which improves the thermal reliability of the dielectric optical coating.