Patents Assigned to Intersil
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Publication number: 20130088209Abstract: A DC-DC voltage converter has a pair of switching transistors to provide an output voltage and are alternately switched in a boost mode of operation responsive to control signals. An inductor is connected to the pair of switching transistor and has an inductor current flowing there through. A current sensor monitors an input current and generates a current sense signal responsive thereto. Control circuitry generates the control signals to the second pair of switching transistors responsive to the current sense signal, the output voltage and a current limit signal, wherein when the current limit signal indicates the inductor current exceeds a current limit the control signals configure the pair of switching transistors to decrease the inductor current.Type: ApplicationFiled: November 28, 2012Publication date: April 11, 2013Applicant: INTERSIL AMERICAS LLCInventor: Intersil Americas LLC
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Patent number: 8416010Abstract: A method of adaptively controlling a charge pump including coupling the charge pump to a control node, toggling a clock input between supply voltage levels to charge an a charge pump output, monitoring the charge pump output, maintaining the control node at a supply voltage level when a supply voltage magnitude does not exceed a threshold level, and adjusting the control node to maintain the charge pump output at a limit level when the supply voltage magnitude exceeds the threshold level. A positive charge pump embodiment charges the output to twice the positive supply voltage up to no more than a limit level. A negative charge pump embodiment charges the output to the same magnitude with opposite polarity as the positive supply voltage, and decreases the output magnitude if the positive supply voltage is above the threshold level. A Zener diode and controlled current mirror may be used for control.Type: GrantFiled: June 17, 2011Date of Patent: April 9, 2013Assignee: Intersil Americas Inc.Inventor: Robert W. Webb
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Patent number: 8415936Abstract: A multiphase DC-DC converter including at least one conversion path, multiple switch capacitance networks, and a multiphase switch controller. Each conversion path includes first and second intermediate nodes. Each switch capacitance network includes a capacitance coupled in parallel with an electronic switch and is coupled to one of the intermediate nodes. The switch controller controls the switch capacitance networks using zero voltage switching. Multiple phases may be implemented as multiple conversion paths each having first and second intermediate nodes coupled to first and second switch capacitance networks, respectively. A single conversion path may be provided with multiple switch capacitance networks coupled to each intermediate node for multiple phases. Alternatively, a common front end with a first intermediate node is coupled to one or more switch capacitance networks followed by multiple back-end networks coupled in parallel for multiple phases.Type: GrantFiled: January 26, 2011Date of Patent: April 9, 2013Assignee: Intersil Americas Inc.Inventor: Zaki Moussaoui
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Patent number: 8416553Abstract: A power supply including an AC input, a filter, a full wave rectifier, a converter, a second rectifier, and a bias system. The filter includes at least one differential capacitor coupled to the AC input. The full wave rectifier develops a DC bus voltage on a DC bus node. The converter includes a controller and operates to convert the DC bus voltage to a regulated output voltage. The second rectifier is coupled to the AC input for developing a DC bias voltage on a DC bias node. The bias system is coupled between the DC bias node and a reference node and provides at least one start-up voltage to the controller, such as a supply voltage or a sense voltage or the like. The bias circuit includes at least one current discharge path for discharging each differential capacitor within a predetermined time period when AC line voltage is removed.Type: GrantFiled: May 26, 2010Date of Patent: April 9, 2013Assignee: Intersil Americas Inc.Inventors: Xiaodong Zhan, Zhixiang Liang, Xiangxu Yu
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Patent number: 8415606Abstract: A configurable photo detector circuit comprises a photo detector array including a plurality of photo detectors coupled to a plurality of amplifiers. A method for programming a detection pattern of the configurable photo detector circuit comprises selecting a first detection pattern for the photo detector array, generating first signals to create the first selected detection pattern, and applying the first generated signals to the photo detector circuit to implement the first selected detection pattern.Type: GrantFiled: December 16, 2011Date of Patent: April 9, 2013Assignee: Intersil Americas Inc.Inventors: Dong Zheng, Daryl Chamberlain
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Patent number: 8416584Abstract: A power supply including a converter, a capacitance, and a hiccup control module. The converter converts an input voltage to both an output voltage and a preliminary standby voltage when in its active state. The capacitance stores the preliminary standby voltage which is charged to an upper voltage level when the converter is in its active state and which is discharged to a lower voltage level when the converter is in its inactive state. During the standby mode, the hiccup control module operates the converter in hiccup mode by toggling between placing the converter into its inactive state when the preliminary standby voltage is charged to the upper voltage level and placing the converter into its active state when the preliminary standby voltage is discharged to the lower voltage level. The hiccup mode of the power supply eliminates a need for a separate standby converter.Type: GrantFiled: May 26, 2010Date of Patent: April 9, 2013Assignee: Intersil Americas Inc.Inventors: Xiaodong Zhan, David B. Bell, Zhixiang Liang, Xiangxu Yu
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Publication number: 20130082670Abstract: A method and system control the adding or dropping of phases in a multiphase voltage regulator. The regulator has an efficiency and this efficiency of the regulator is calculated for a given number of phases being activated from an output voltage, input voltage, output current, and duty cycle of the regulator. The efficiency of the regulator is also calculated if a phase is added using the derivative of the duty cycle as a function of the output current. The efficiency of the regulator is further calculated if a phase is dropped using the derivative of the duty cycle as a function of the output current. From these operations of calculating, a phase is either added, dropped, or the phase is maintained at its current value to thereby optimize the efficiency of the regulator.Type: ApplicationFiled: November 26, 2012Publication date: April 4, 2013Applicant: INTERSIL AMERICAS INC.Inventor: INTERSIL AMERICAS INC.
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Publication number: 20130081266Abstract: An embodiment of an electronic component includes a circuit element disposed within a package, which includes a surface and at least one standoff protruding from the surface. For example, where the circuit element is an inductor in a power supply, the standoff may allow one to mount the inductor component over another component, such as a transistor component. Therefore, the layout area of such a power supply may be smaller than the layout area of a power supply in which the inductor and transistor components are mounted side by side.Type: ApplicationFiled: November 26, 2012Publication date: April 4, 2013Applicant: INTERSIL AMERICAS LLCInventor: INTERSIL AMERICAS LLC
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Patent number: 8405368Abstract: A phase current sharing network for a current mode multiphase switching regulator. The multiphase switching regulator includes switching networks for developing phase currents of switching phase networks controlled by pulse control signals for converting an input voltage to an output voltage. The regulator develops the pulse control signals based on current control values and at least one trigger value. The phase current sharing network includes conversion networks and a phase current combining network. Each conversion network provides a phase current value based on a corresponding phase current, such as by directly or indirectly measuring real current or by synthetically developing the phase current value. The phase current combining network develops an average phase current value based on the phase current values, and subtracts the average phase current value from each phase current value to provide the current control values used to control the switching networks.Type: GrantFiled: September 9, 2010Date of Patent: March 26, 2013Assignee: Intersil Americas Inc.Inventors: Steven P. Laur, Rhys S. A. Philbrick
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Patent number: 8400134Abstract: Circuitry and methodology for tracking the maximum power point (MPP) of a solar panel is disclosed. The voltage and current generated by the solar panel are monitored and used to generate a pulse signal for charging a capacitor. The changes in the voltage and current generated by the solar panel are also monitored, and that information is used to generate a pulse signal for discharging the capacitor. The charging and the discharging pulse signals are used to charge and discharge the capacitor. A reference signal indicative of the charge level of the capacitor is generated. As the current and voltage generated by the solar panel approach the maximum power point (MPP), the frequency of the discharging pulse signal becomes progressively higher, so that the capacitor charging occurs in progressively smaller increments. When the MPP is reached, the reference signal level becomes steady because the charge level of the capacitor becomes steady.Type: GrantFiled: March 3, 2010Date of Patent: March 19, 2013Assignee: Intersil Americas Inc.Inventors: Zaki Moussaoui, Weihong Qiu, Jun Liu
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Publication number: 20130057229Abstract: The various embodiments may include a power supply having a first loop in communication with a power stage of the power supply. A second loop in communication with the first loop may generate a negative reactance value that increases a power factor for the power supply to approximately one. A power supply may also include a rectifier coupleable to an input supply. A power factor compensation circuit coupled to the rectifier may generate a negative reactance. The negative reactance may reduce a phase angle between a current and a voltage provided to the input supply. A method may include sensing an output of a power supply, and adjusting the sensed value. The adjusted value may be compared to a reference value to generate an error value. The error value and a negative reactance value may be combined and the result may be provided to the power supply.Type: ApplicationFiled: December 9, 2011Publication date: March 7, 2013Applicant: INTERSIL AMERICAS INC.Inventors: Manjing XIE, Zhixiang LIANG
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Patent number: 8390740Abstract: Provided herein are methods and systems that provide automatic compensation for frequency attenuation of a video signal transmitted over a cable. In accordance with an embodiment, a system includes an equalizer and a compensation controller. The equalizer receives a video signal that was transmitted over a cable, provides compensation for frequency attenuation that occurred during the transmission over the cable, and outputs a compensated video signal. The compensation controller automatically adjusts the compensation provided by the equalizer based on comparisons of one or more portions of the compensated video signal to one or more reference voltage levels.Type: GrantFiled: March 26, 2009Date of Patent: March 5, 2013Assignee: Intersil Americas Inc.Inventors: David W. Ritter, Robert D. Zucker, Warren Craddock
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Patent number: 8390743Abstract: Systems and methods for the synchronization and display of video input signals. The input signals, associated with input channels, are received by a controller. On a frame-by-frame basis, the controller controls the writing of the input signals to, and the reading of the input signals from, a memory. A frame rate control module controls frame-level synchronization between the writing operations and reading operations of the controller so that when a frame is written to the memory is not simultaneously read from the memory. The controller writes video frames for each input channel to, and reads video frames for each input channel from, the memory on a channel-by-channel basis such that the video frames corresponding to each input channel are read and written independently of one another. This allows the input signals to be unsynchronized with one another without harming the writing operations, reading operations, and display of the input signals.Type: GrantFiled: August 31, 2011Date of Patent: March 5, 2013Assignee: Intersil Americas Inc.Inventors: Hown Cheng, Do Hwan Lim, Byungdae Jeong
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Patent number: 8385030Abstract: Provided herein are circuits, systems and methods that monitor for a fault within a multi-phase DC-DC converter. This can include monitoring the channels of the DC-DC converter for way out of balance (WOB) conditions, and monitoring for a component fault in dependence on detected WOB conditions. A fault can be detected if, during a predetermined period of time, one of the WOB conditions occurs at least a specified amount of times more than another one of the WOB conditions. The DC-DC converter and/or another circuit can be shut-down in response to a fault being detected. Additionally, or alternatively, a component fault detection signal can be output in response to a fault being detected.Type: GrantFiled: January 21, 2010Date of Patent: February 26, 2013Assignee: Intersil Americas Inc.Inventor: Timothy Maher
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Patent number: 8385036Abstract: An electronic system is disclosed, which includes a connector unit to communicate data with a host system, an electronic circuit to store the data, and a switch to convey the data to and from the electronic circuit via the connector unit. The switch includes a negative voltage protection unit coupled to the connector unit, and a transistor switch coupled to the negative voltage protection unit, the connector unit, and the electronic circuit. The negative voltage protection unit forces the transistor switch off if a negative voltage is detected.Type: GrantFiled: April 15, 2010Date of Patent: February 26, 2013Assignee: Intersil Americas Inc.Inventor: Donald Giles Koch
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Patent number: 8384650Abstract: A multi-reference voltage generator includes an interface controller, a first bank of N m-bit registers and a second bank of N m-bit registers. A first multiplexer has inputs connected to outputs of the first and second bank of registers. An m-bit digital-to-analog (DAC) has an m-bit parallel input connected to an output of the first multiplexer. An analog demultiplexer has an input connected to an analog output of the m-bit DAC. Each voltage storage device in a first group of N voltage storage devices is connected to a corresponding output of the analog demultiplexer. Similarly, each voltage storage device in a second group of N voltage storage devices is connected to a corresponding output of the analog demultiplexer. N further multiplexers each have a first input connected to an output of a corresponding one of the voltage storage devices in the first group and a second input connected to an output of a corresponding one of the voltage storage devices in the second group.Type: GrantFiled: February 2, 2011Date of Patent: February 26, 2013Assignee: Intersil Americas Inc.Inventor: Chor Yin Chia
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Patent number: 8384832Abstract: Systems, methods and devices provide for fast and power efficient transfer of three color data words (e.g., a M-bit red color word, a M bit green color word and a M-bit blue color word) per pixel from a controller to a laser diode driver (LDD). First and second transfer words are produced based on the three color data words. The first transfer word is transferred from the controller to the LDD and stored at LDD in response to a low-to-high portion of a cycle of a data transfer clock, and the second transfer word is transferred and stored in response to a high-to-low portion of a cycle of the data transfer clock. The first, second and third color data words are reproduced by the LDD in dependence on the first and second received transfer words. First, second and third DACs of the LDD are driven with the first color data word, the second color data word, and the third color data word. Three light sources (e.g., red, green and blue laser diodes or LEDs) are driven with output currents of the DACs.Type: GrantFiled: July 27, 2010Date of Patent: February 26, 2013Assignee: Intersil Americas Inc.Inventors: Alexander Fairgrieve, D. Stuart Smith
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Publication number: 20130043940Abstract: Embodiments disclosed herein provide for a circuit including first die having an active side and a backside, wherein the first die is flip-chip mounted to a carrier. The circuit also includes a second die stacked on the backside of the first die, wherein the second die is stacked on the first die such that a backside of the second die is facing the backside of the first die and an active side of the second die faces away from the first die.Type: ApplicationFiled: January 26, 2012Publication date: February 21, 2013Applicant: INTERSIL AMERICAS LLCInventors: Francois Hebert, Steven R. Rivet, Michael Althar, Peter Oaklander
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Patent number: 8378650Abstract: Provided herein are circuits, systems and methods that monitor for way out of balance (WOB) conditions within a multi-phase DC-DC converter, and adjust a balance between currents through channels of the DC-DC converter, in dependence on detected WOB conditions.Type: GrantFiled: January 21, 2010Date of Patent: February 19, 2013Assignee: Intersil Americas Inc.Inventor: Timothy Maher
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Patent number: RE44140Abstract: In accordance with the invention, there are various methods of making an integrated circuit comprising a bipolar transistor. According to an embodiment of the invention, the bipolar transistor can comprise a substrate, a collector comprising a plurality of alternating doped regions, wherein the plurality of alternating doped regions alternate in a lateral direction from a net first conductivity to a net second conductivity, and a collector contact in electrical contact with the collector. The bipolar transistor can also comprise a heavily doped buried layer below the collector, a base in electrical contact with a base contact, wherein the base is doped to a net second conductivity type and wherein the base spans a portion of the plurality of alternating doped regions, and an emitter disposed within the base, the emitter doped to a net first conductivity, wherein a portion of the alternating doped region under the emitter is doped to a concentration of less than about 3×1012 cm?2.Type: GrantFiled: November 14, 2011Date of Patent: April 9, 2013Assignee: Intersil Americas Inc.Inventor: James D. Beasom