Abstract: A method for the production of a photovoltaic device, for instance a solar cell, is disclosed. In one aspect, the method comprises providing a substrate having a front main surface and a rear surface. The method further comprises depositing a dielectric layer on the rear surface, wherein the dielectric layer has a thickness larger than about 100 nm. The method further comprises depositing a passivation layer comprising hydrogenated SiN on top of the dielectric layer and forming back contacts through the dielectric layer and the passivation layer. In another aspect, corresponding photovoltaic devices, for instance solar cell devices, are also disclosed.

Abstract: One inventive aspect relates to a reconfigurable cavity resonator. The resonator comprises a cavity delimited by metallic walls. The resonator further comprises a coupling device for coupling an electromagnetic wave into the cavity. The resonator further comprises a tuning element for tuning a resonance frequency at which the electromagnetic wave resonates in the cavity. The tuning element comprises one or more movable micro-electromechanical elements with an associated actuation element located in their vicinity for actuating each of them between an up state and a down state. The movable micro-electromechanical elements at least partially have a conductive surface and are mounted within the cavity.

Abstract: The present disclosure is related to non-volatile memory devices comprising a reversible resistivity-switching layer used for storing data. The resistivity of this layer can be varied between at least two stable resistivity states such that at least one bit can be stored therein. In particular this resistivity-switching layer is a metal oxide or a metal nitride. A resistivity-switching non-volatile memory element includes a resistivity-switching metal-oxide layer sandwiched between a top electrode and a bottom electrode. The resistivity-switching metal-oxide layer has a gradient of oxygen over its thickness. The gradient is formed in a thermal oxidation step. Set and reset voltages can be tuned by using different oxygen gradients.

Abstract: A method for determining programming/erase conditions and a method for operating a charge-trapping semiconductor device are disclosed. Programming and erase conditions are determined such that a first net charge distribution variation profile, upon going from programmed to erased state, is substantially the opposite of a second net charge distribution variation profile, upon going from erased to programmed state.

Abstract: A method of manufacturing a dual work function semiconductor device is disclosed. In one aspect, the method comprises providing a first metal layer over a first electrode in a first region, and at least a first work function tuning element. The method further comprises providing a second metal layer of a second metal in a second region at least over a second electrode. The method further comprises performing a first silicidation of the first electrode and a second silicidation of the second electrode simultaneously.

Abstract: A method and apparatus for removing a first liquid from a surface of a substrate is provided. A second liquid is supplied to at least part of a surface of a substrate having a rotary movement. The rotary movement has a center of rotation and an edge of rotation. The second liquid is directed from the center of rotation to the edge of rotation using a nozzle. A dry zone is created on the substrate as the position of the spray moves from the center of rotation to the edge of rotation. As a result, the first liquid and the second liquid are removed from the surface of the substrate.

Abstract: A method and system for measuring contamination of a lithographic element is disclosed. In one aspect, the method comprises providing a first lithographical element in a process chamber. The method further comprises providing a second lithographical element in the process chamber. The method further comprises covering part of the first lithographical element providing a reference region. The method further comprises providing a contaminant in the process chamber. The method further comprises redirecting an exposure beam via the test region of the first lithographical element towards the second lithographical element whereby at least one of the lithographical elements gets contaminated by the contaminant. The method further comprises measuring the level of contamination of the at least one contaminated lithographical element in the process chamber.

Abstract: An intermediate probe structure for atomic force microscopy is disclosed. The probe structure comprises a semiconductor substrate with one or more moulds formed on a surface of one side of the substrate. The probe structure further comprises one or more probe configurations formed on the one side of the semiconductor substrate, wherein each probe configuration comprises a contact region and at least one set of a probe tip and a cantilever. The probe structure further comprises one or more holders attached to each of the contact regions, wherein the surface area of each contact region is smaller in size than the surface area of the holder which is attached to the contact region.

Abstract: A method of designing a lithographic mask for use in lithographic processing of a substrate is disclosed. The lithographic processing comprises irradiating mask features of a lithographic mask using a predetermined irradiation configuration. In one aspect, the method comprises obtaining an initial design for the lithographic mask comprising a plurality of initial design features having an initial position. The method further comprises applying at least one shift to at least one initial design feature and deriving there from an altered design so as to compensate for shadowing effects when irradiating the substrate using a lithographic mask corresponding to the altered design in the predetermined irradiation configuration. Also disclosed herein are a corresponding design, a method of setting up lithographic processing, a system for designing a lithographic mask, a lithographic mask, and a method of manufacturing it.

Abstract: The invention relates to a method for cleaning semiconductor surfaces to achieve to removal of all kinds of contamination (particulate, metallic and organic) in one cleaning step. The method employs a cleaning solution for treating semiconductor surfaces which is stable and provokes less or no metal precipitation on the semiconductor surface.

Abstract: A method is disclosed for lithographic processing. In one aspect, the method comprises obtaining a resist material with predetermined resist properties. The method further comprises using the resist material for providing a resist layer on the device to be lithographic processed. The method further comprises illuminating the resist layer according to a predetermined pattern to be obtained. The obtained resist material comprises a tuned photo-acid generator component and/or a tuned quencher component and/or a tuned acid mobility as to reduce watermark defects on the lithographic processed device. In another aspect, a corresponding resist material, a set of resist materials, use of such materials and a method for setting up a lithographic process are disclosed.

Abstract: Methods for the quantification of hydrophilic properties of a porous material, as well as determining a depth of damage of a porous material are disclosed. An example method includes performing a first ellipsometric measurement on the porous material using a first adsorptive having a first wetting angle. The example method further includes performing a second ellipsometric measurement on the porous material using a second adsorptive having a second wetting angle, wherein the first and second wetting angles are different towards the porous material. The hydrophilic properties of the porous material are determined based, at least in part, on the first and second ellipsometric measurements.

Abstract: A semiconductor device is disclosed. In one aspect, the device comprises a channel area, the channel area comprising a channel layer in which charge carriers can move when the transistor is turned on, in order to pass a current through the transistor. The device further comprises a source area and a drain area contacting the channel layer for providing current to and from the channel layer. The method further comprises a gate electrode, preferably provided with a gate dielectric between the gate electrode and the channel layer. The channel layer may comprise a III-V material, and the source and drain areas comprise SiGe, being SixGe1-x, with x between 0 and 100%, arranged so that heterojunctions are present between III-V material and SiGe, wherein the heterojunctions are oriented so as to intersect with the gate dielectric or the gate electrode.

Abstract: A method for forming deep trench or via airgaps in a semiconductor substrate is disclosed comprising the steps of patterning a hole in the substrate, partly fill said hole with a sacrificial material (e.g. poly-Si), depositing spacers on the sidewalls of the unfilled part of the hole (e.g. TEOS) to narrow the opening, removing through said narrowed opening the remaining part of the sacrificial material (e.g. by isotropic etching) and finally sealing the opening of the airgap by depositing a conformal layer (TEOS) above the spacers. The method of forming an airgap is demonstrated successfully for use as deep trench isolation structures in BiCMOS devices.

Abstract: An electronic device and a process for manufacturing the same are disclosed. In one aspect, the device comprises an electrode comprising a metal compound selected from the group of tantalum carbide, tantalum carbonitride, hafnium carbide and hafnium carbonitride. The device further comprises a high-k dielectric layer of a hafnium oxide comprising nitrogen and silicon, the high-k dielectric layer having a k value of at least 4.0. The device further comprises a nitrogen and/or silicon and/or carbon barrier layer placed between the electrode and the high-k dielectric layer. The nitrogen and/or silicon and/or carbon barrier layer comprises one or more metal oxides, the metal of the metal oxides being selected from the group of lanthanides, aluminium or hafnium.

Abstract: An interconnect module and a method of manufacturing the same. The method of making an interconnect module on a substrate comprises forming an interconnect section on the substrate. The interconnect section comprises at least two metal interconnect layers separated by a dielectric layer. The method further comprises forming a passive device on the substrate at a location laterally adjacent to the interconnect section. The passive device comprises at least one moveable element comprising a metal layer. The method further comprises forming the metal layer and one of the at least two metal interconnect layers from substantially the same material.

Abstract: The present invention relates to a method for the patterning of a stack of layers on a surface with high topography. A method of the present invention can be used for gate patterning for multiple Gate FETs (MuGFETs), for patterning of the control gate in non-volatile memory applications, and for the patterning of the poly emitter in BiCMOS devices. The present invention also relates to a device prepared by a method of the invention.

Abstract: A method is provided for the patterning of a stack comprising elements that do not form volatile compounds during conventional reactive ion etching. More specifically the element(s) are Lanthanide elements such as Ytterbium (Yb) and the patterning preferably relates to the dry etching of silicon and/or germanium comprising structures (e.g. gates) doped with a Lanthanide e.g. Ytterbium (Yb doped gates). In case the silicon and/or germanium comprising structure is a gate electrode the silicon and/or germanium is doped with a Lanthanide (e.g. Yb) for modeling the work function of a gate electrode.

Abstract: A hardware memory architecture or arrangement suited for multi-processor systems or arrays is disclosed. In one aspect, the memory arrangement includes at least one memory queue between a functional unit (e.g., computation unit) and at least one memory device, which the functional unit accesses (for write and/or read access).

Abstract: A method for the production of a photovoltaic device is disclosed. In one aspect, the method comprises providing a carrier substrate. The method further comprises forming a crystalline semiconductor layer on the substrate. The method further comprises carrying out hydrogen passivation of the crystalline semiconductor layer. The method further comprises creating an emitter on the surface of the passivated crystalline semiconductor layer.