Abstract: An optical waveguide to fiber coupler comprises a substrate, a first waveguide and a second waveguide. The first and second waveguides are formed on the substrate and intersect at a right angle. A diffraction grating structure is formed at the intersection of the first and second waveguides, such that, when the coupler is physically abutted with a single mode optical fiber, in operation, a polarization split is obtained that couples orthogonal modes from the single-mode optical fiber into single identical modes in the first and second waveguides. Also, employing the coupler in optical polarization diverse applications provides for implementing a polarization insensitive photonic integrated circuit using such diffraction grating structures, such as, for example, photonic crystals.

Abstract: A system and method for guiding a beam of electromagnetic radiation is disclosed. The system includes at least a first stack of dielectric layers, the first stack comprising at least a first substack, a second substack and a third substack, the third substack separating said first and second substack, the first substack comprising at least one dielectric layer, the second substack comprises at least one dielectric layer, the third substack comprises at least one dielectric layer. The dielectric layers of the first substack and the second substack equidistant from the third substack have the same refractive index.

Abstract: A planar high-density EEPROM split gate memory structure, is formed using two poly-layers and chemical-mechanical-polishing processes. Stripes of contiguous poly lines, alternately formed in one of the two poly-layers, constitute the memory structure. Source and drain regions are formed self-aligned to the outer borders of this memory structure. Depending on the biasing scheme a poly line is used as the select gate of the memory cell while an adjacent poly line is used as program gate, so to have charge stored underneath this adjacent poly line using source-side-injection of charge carriers. The other poly lines are biased to form conductive channels between the select and program gate to the source and drain regions. These conductive channels form soft source and drain regions next to the select and program gate in use.

Abstract: A method and an apparatus for removing a liquid, i.e a wet processing liquid, from a surface of at least one substrate is disclosed. A liquid is supplied on a surface of substrate. Simultaneously or thereafter besides the liquid also a gaseous substance can be supplied thereby creating at least locally a sharply defined liquid-vapor boundary. The gaseous substance and the liquid can be selected such that the gaseous substance is miscible with the liquid and when mixed with the liquid yields a mixture having a surface tension lower than that of the liquid. According to the invention, the substrate is subjected to a rotary movement at a speed to guide said liquid-vapor boundary over said substrate thereby removing said liquid from said substrate.

Abstract: A device for detecting an analyte in a sample comprising an active layer comprising at least a dielectric material, a source electrode, a drain electrode and a semiconducting substrate which acts as current pathway between source and drain. The conductivity of said semiconducting layer can be influenced by the interaction of the active layer with the sample containing the analyte to detect. The device is fabricated such that properties like low price, disposability, reduced drift of the device and suitability for biomedical and pharmaceutical applications are obtained. To fulfill these requirements, the device described in this application will be based on organic-containing materials.

Abstract: A scaleable device concept and particularly a method for fabrication thereof is disclosed, which allows for a minimal well-controlled gate overlap by using low resistivity source/drain extension regions with shallow junctions. By using such shallow junctions, which are obtained using L-shaped spacers, the gate overlap is no longer dependent on the junction depth of the source/drain contact regions. Particularly the L-shaped spacers are used to locally reduce the penetration depth of the source/drain implantation in the substrate. This concept is particularly interesting for FET's having a channel length below 0.25 &mgr;m because this approach broadens the process window of the silicidation process of the source/drain contact regions. Moreover, the extension regions have to be subjected only to a limited thermal budget.

Abstract: The present invention is a method for programming SSI cells or an array of said cells. The method achieves very fast programming while consuming only a very small amount of power, which paves the way for new applications such as battery-operated systems, page-mode programming for very high data throughput. The method also allows for the bitline voltage to be increased internally on the chip in order to circumvent the efficiency decrease associated with supply voltage scaling. By exploring the SSI mechanism in the subthreshold regime, an optimum value for the CG voltage is found for which the gate current is no longer maximized, but the energy consumed from the power supply is minimized and the injection efficiency during programming is maximized. The programming of a memory cell in this regime, where the gate current is a very steep function of the CG voltage, is, however, still achieved in a few microseconds while consuming only a very small cell current in the range of nanoamperes.

Abstract: Method of preparing on a solar cell the top contact pattern which consists of a set of parallel narrow finger lines and wide collector lines deposited essentially at right angles to the finger lines on the semiconductor substrate, characterized in that it comprises at least the following steps: (a) screen printing and drying the set of contact finger lines; (b) printing and drying the wide collector lines on the top of the set of finger lines in a subsequent step; (c) firing both finger lines and collector lines in a single final step in order to form an ohmic contact between the finger lines and the semiconductor substrate and between the finger lines and the wide collector lines.