Abstract: A method for selective deposition of self-assembled monolayers to the surface of a substrate for use as a diffusion barrier layer in interconnect structures is provided comprising the steps of depositing a first self-assembled monolayer to said surface, depositing a second self-assembled monolayer to the non-covered parts of said surface and subsequently heating said substrate to remove the first self-assembled monolayer. The method of selective deposition of self-assembled monolayers is applied for the use as diffusion barrier layers in a (dual) damascene structure for integrated circuits.

Abstract: A method of manufacturing a semiconductor device with at least a first dielectric material and a second dielectric material is disclosed. In one aspect, the method comprises providing a first dielectric material on a substrate. The method further comprises providing a patterned sacrificial layer covering the first dielectric material in at least a first region of the substrate. The method further comprises providing a second dielectric material covering the patterned sacrificial layer in the first region and covering the first dielectric material in at least a second region, the second region being different from the first region. The method further comprises patterning the second dielectric material such that the patterned second dielectric material covers the first dielectric material in the second region but not the patterned sacrificial layer in the first region. The method further comprises removing the patterned sacrificial material.

Abstract: A method for forming doped metal-semiconductor compound regions in a substrate is disclosed. In one aspect, a method for forming silicide regions in a substrate comprises partially regrowing an upper amorphous region on top of a crystalline part of the substrate, after having doped the upper amorphous region, to form a regrown region, thereby leaving a remaining upper amorphous region in between the regrown region and the major surface of the substrate. The remaining upper amorphous region is used for forming the metal-semiconductor compound.

Abstract: One inventive aspect relates a variable capacitor comprising first and second electrically conductive electrodes, arranged above a support structure and spaced apart from each other and defining the capacitance of the capacitor. At least one of the electrodes comprises at least one bendable portion. The bendable portion(s) are actuated by a DC voltage difference which is applied over the electrodes to vary the capacitance. In preferred embodiments, the support structure comprises a layer of higher permittivity than the atmosphere surrounding the electrodes and the electrodes configure as an interdigitated structure upon actuation. Also disclosed is a 2-mask process for producing such capacitors.

Abstract: A method for doping a multi-gate device is disclosed. In one aspect, the method comprises patterning a fin in a substrate, depositing a gate stack, and doping the fin. The process of doping the fin is done by depositing a blocking mask material at least on the top surface of the fin after the patterning of the gate stack. After the deposition of the blocking mask material dopant ions are implanted whereby the blocking mask material partially or completely blocks the top surface of the fin from these dopant ions.

Abstract: A method for doping a fin-based semiconductor device is disclosed. In one aspect, the method comprises patterning at least one fin, each fin comprising a top surface and a left sidewall surface and a right sidewall surface. The method further comprises providing a first target surface being the right sidewall of a first block of material. The method further comprises scanning a first primary ion beam impinging on the first target surface with an incident angle ? different from zero degrees and thereby inducing a first secondary ion beam, and doping at least the left sidewall surface and possibly the top surface of the fin opposite to the first target surface with the first secondary ion beam.

Abstract: One inventive aspect relates to a reconfigurable cavity resonator. The resonator comprises a cavity delimited by metallic walls. The resonator further comprises a coupling device for coupling an electromagnetic wave into the cavity. The resonator further comprises a tuning element for tuning a resonance frequency at which the electromagnetic wave resonates in the cavity. The tuning element comprises one or more movable micro-electromechanical elements with an associated actuation element located in their vicinity for actuating each of them between an up state and a down state. The movable micro-electromechanical elements at least partially have a conductive surface and are mounted within the cavity.

Abstract: The present invention is related to a method for controlled transport of magnetic beads between a position X and different position Y, such that the magnetic beads are manipulated or transported by applying successively a series of N local magnetic fields which have magnetic field gradients different from 0 in the neighborhood of said magnetic beads. Each of these N local magnetic fields is generated by a single current carrying structure, in which the current density is not constant. The invention generally relates to application in the domain of biochips and micro-arrays, used in diagnostics, genetics and molecular studies.

Abstract: A multiple gate semiconductor device. The device includes at least two gates. The dopant distribution in the semiconductor body of the device varies from a low value near the surface of the body towards a higher value inside the body of the device.

Abstract: Dielectric material compositions comprising HfO2 and a second compound are disclosed. The compositions are characterized by at least a part of the compositions being in a cubic crystallographic phase. Further, semiconductor based devices comprising such dielectric material compound and method for forming such compounds are disclosed.

Abstract: A charge pump circuit and method for supplying power. The charge pump circuit includes a first circuit receiving at least one low voltage signal and generating an output voltage signal. The charge pump circuit also includes a second circuit receiving a clock signal and the output voltage signal. The second circuit sends a request signal based on a comparison of the output voltage signal with two reference voltage signals, where the two reference voltage signals are derived from two supply voltage signals having a substantially constant potential difference. The charge pump circuit further includes a high voltage generator receiving the request signal and sending the two supply voltage signals to the first circuit and the second circuit. The high voltage generator adjusts the voltage potentials of the two supply voltage signals such that the voltage potential of the output voltage signal falls between the voltage potentials of the two reference voltage signals.

Abstract: Coding, transcoding and iterative filtering methods and apparatus are described wherein a 2D FIFO is used to implement CACLA processing, and wherein the processing methods are block-oriented. A block-by-block processed input image or input coded image, which is delayed in an arbitrary number of lines and columns, is provided such that the output image is produced in a block-by-block schedule at a reduced or minimal memory access and memory size cost. A 2D FIFO which is memory-efficient in image block coding and decoding applications is described. The 2D FIFO has an associated scheduling mechanism for enabling delay of a block-by-block coded input signal, such as an image, in an arbitrary number of lines and columns, such that the output image is produced in a block-by-block schedule.

Abstract: Methods for the quantification of hydrophilic properties of a porous material, as well as determining a depth of damage of a porous material are disclosed. An example method includes performing a first ellipsometric measurement on the porous material using a first adsorptive having a first wetting angle. The example method further includes performing a second ellipsometric measurement on the porous material using a second adsorptive having a second wetting angle, wherein the first and second wetting angles are different towards the porous material. The hydrophilic properties of the porous material are determined based, at least in part, on the first and second ellipsometric measurements.

Abstract: One aspect of the invention discloses a method of determining the dopant profile of doped regions in a semiconductor substrate. A pump laser is used to create excess carriers in this semiconductor substrate. The excess carrier concentration will influence the reflection of a probe laser. From the reflected probe laser not only the bulk components but also the near-surface components are eliminated to only yield the bulk components.

Abstract: A method of producing a semiconductor device on a silicon on insulator (SOI) substrate is disclosed. In one aspect, the method comprises providing a device with a monocrystalline semiconductor layer on an insulating layer; providing a mask on the semiconductor layer to provide first shielded portions and first unshielded portions, amorphizing the first unshielded portions to yield first amorphized portions of the monocrystalline semiconductor layer, implanting a first dopant in the first amorphized portions, applying a first solid phase epitaxial regrowth action to the semiconductor device while using the first shielded portions as monocrystalline seeds.

Abstract: A method for the production of airgaps in a semiconductor device and device produced therefrom. The formation of airgaps is accomplished, in part, by chemically and/or mechanically changing the properties of a first dielectric layer locally, such that at least part of said first dielectric layer is converted locally and becomes etchable by a first etching substance. The local conversion of the dielectric material may be achieved during anisotropic etching of the material in oxygen containing plasma or ex-situ by performing an oxidizing step (e.g., a UV/ozone treatment or supercritical carbon dioxide with addition of an oxidizer). Formation of airgaps is achieved after creation of conductive lines and, alternatively, a barrier layer by a first etching substance. The airgaps are formed in a dual damascene structure, near the vias and/or the trenches of the damascene structure.

Abstract: Non-volatile memory devices are disclosed. In a first example non-volatile memory device, programming and erasing of the memory device is performed through the same insulating barrier without the use of a complex symmetrical structure. In the example device, programming is accomplished by tunneling negative charge carriers from a charge supply region to a charge storage region. Further in the example device, erasing is accomplished by tunneling positive carriers from the charge supply region to the charge storage region. In a second example non-volatile memory device, a charge storage region with spatially distributed charge storage region is included. Such a charge storage region may be implemented in the first example memory device or may be implemented in other memory devices. In the second example device, programming is accomplished by tunneling negative charge carriers from a charge supply region to the charge storage region.

Abstract: Damascene stacks for use in semiconductor devices and methods for making such stacks are disclosed. An example damascene stack includes a substantially planar lower liner layer and a patterned sacrificial dielectric layer disposed on top of the lower liner layer, where the patterned sacrificial dielectric layer includes an interconnect structure of the damascene stack. The example damascene stack further includes a substantially planar upper liner layer disposed on top of the patterned sacrificial dielectric layer, where the upper liner layer being formed of a material that is resistant to etching by a first etch compound. There is at least one plug-hole in the upper liner layer, where the at least one plug-hole is (i) adjacent to the interconnect structure and (ii) formed by locally converting a portion of the upper liner layer to be etchable by the first etch compound and removing the locally converted portion of the upper liner layer using the first etch compound.

Abstract: A method for the production of airgaps in a semiconductor device and device produced therefrom. The formation of airgaps is accomplished, in part, by chemically and/or mechanically changing the properties of a first dielectric layer locally, such that at least part of said first dielectric layer is converted locally and becomes etchable by a first etching substance. The local conversion of the dielectric material may be achieved during anisotropic etching of the material in oxygen containing plasma or ex-situ by performing an oxidizing step (e.g., a UV/ozone treatment or supercritical carbon dioxide with addition of an oxidizer). Formation of airgaps is achieved after creation of conductive lines and, alternatively, a barrier layer by a first etching substance. The airgaps are formed in a dual damascene structure, near the vias and/or the trenches of the damascene structure.

Abstract: A method of controlling an internal stress in a polycrystalline silicon-germanium layer deposited on a substrate. The method includes selecting a deposition pressure that is at or below atmospheric pressure and selecting a deposition temperature that is no greater than 700° C. The deposition pressure and the deposition temperature are selected so as to achieve an internal stress in the silicon-germanium layer that is within a predetermined range.