Abstract: A method for manufacturing a dual workfunction semiconductor device and the device made thereof are disclosed. In one aspect, the method includes manufacturing a first transistor in a first region and a second transistor in a second region of a substrate, the first transistor including a first gate stack, the first gate stack having a first gate dielectric capping layer and a first metal gate electrode layer. The second gate stack is similar to the first gate stack. The method includes applying a first thermal budget to the first gate dielectric capping layer and a second thermal budget to the second gate dielectric capping material to tune the workfunction of the first and second gate stack, the first thermal budget being smaller than the second thermal budget such that after the thermal treatment the first and the second gate stack have different work functions.

Abstract: A method for manufacturing a MuGFET ESD protection device having a given layout by means of a given manufacturing process, the method comprising selecting multiple interdependent layout and process parameters of which a first set are fixed by said manufacturing process and a second set are variable, selecting multiple combinations of possible layout and process parameter values which meet predetermined ESD constraints; determining an optimum value for at least one other parameter in view of a predetermined design target apart from the predetermined ESD constraints; determining values for fin width (Wfin), gate length (LG) and number of fins (N) on the basis of the optimum value; and manufacturing said MuGFET ESD protection device using the given manufacturing and process values.

Abstract: A method for removing impurities from at least one semiconductor device layer during manufacturing of a semiconductor device is disclosed. The semiconductor device layer has a compound semiconductor material and/or germanium. Each heating process performed during the manufacturing of the semiconductor device after provision of the semiconductor device layer has a low thermal budget determined by temperatures equal to or lower than about 900° C. and time periods equal to or lower than about 5 minutes. In one aspect, the method includes providing a germanium gettering layer with a higher solubility for the impurities than the semiconductor device layer. The germanium gettering layer is provided at least partly in direct or indirect contact with the at least one semiconductor device layer, such that impurities can diffuse from the at least one semiconductor device layer to the germanium gettering layer.

Abstract: A method for producing one or more nMOSFET devices and one or more pMOSFET devices on the same semiconductor substrate is disclosed. In one aspect, the method relates to the use of a single activation anneal that serves for both Si NMOS and Ge pMOS. By use of a solid phase epitaxial regrowth (SPER) process for the Si nMOS, the thermal budget for the Si NMOS can be lowered to be compatible with Ge pMOS.

Abstract: A technique is described for the preparation of polymers according to a process in which the starting compound of formula (I) is polymerized in the presence of a base in an organic solvent. No end chain controlling agents are required during the polymerisation to obtain soluble precursor polymers. The precursor polymer such obtained comprises structural units of the formula (II). In a next step, the precursor polymer (II) is subjected to a conversion reaction towards a soluble or insoluble conjugated polymer by thermal treatment. The arylene or heteroarylene polymer comprises structural units of the formula III. In this process the dithiocarbamate group acts as a leaving group and permits the formation of a precursor polymer of structural formula (II), which has an average molecular weight from 5000 to 1000000 Dalton and is soluble in common organic solvents. The precursor polymer with structural units of formula (II) is thermally converted to the conjugated polymer with structural formula (III).

Abstract: A dual workfunction semiconductor device and a device made thereof is disclosed. In one aspect, the device includes a first gate stack in a first region and a second gate stack in a second region. The first gate stack has a first effective workfunction, and the second gate stack has a second effective workfunction different from the first effective workfunction. The first gate stack includes a first gate dielectric capping layer, a gate dielectric host layer, a first metal gate electrode layer, a barrier metal gate electrode, a second gate dielectric capping layer, and a second metal gate electrode. The second gate stack includes a gate dielectric host layer, a first metal gate electrode, a second gate dielectric capping layer, and a second metal gate electrode.

Abstract: Systems and methods for controlling a micro electromechanical device using power actuation are disclosed. The disclosed micro electromechanical systems comprise at least one electrostatically actuatable micro electromechanical device and an actuation device. The micro electromechanical device comprises a first conductor and a second conductor having a moveable portion which in use may be attracted by the first conductor as a result of a predetermined actuation power. The actuation device comprises a high frequency signal generator for generating at least part of the actuation power by means of a predetermined high frequency signal with a frequency higher than the mechanical resonance frequency of the moveable portion of the micro electromechanical device.

Abstract: The present invention is related to a slurry composition for polishing copper integrated with tungsten containing barrier layers and its use in a CMP method. The present invention is also related to a method for polishing copper integrated with tungsten containing barrier layers by means of an aqueous solution containing abrasive particles, an inorganic acid such as HNO3 as etchant for copper that prevents galvanic corrosion of the tungsten containing metal barrier and at least one organic compound to provide sufficient copper corrosion inhibition.

Abstract: A method is provided for incorporating zeolite crystals in patterned structures, the zeolite crystals having pores (channels) with an orientation which is defined by the topology of the zeolite crystal type and the geometry of the patterned structure, resulting in pores parallel with the length axis of the patterned structures. The patterned structures may be vias (vertical contacts) and trenches (horizontal lines) in a semiconductor substrate. These zeolite crystals can advantageously be used for dense and aligned nanocarbon growth or in other words growth of carbon nanostructures such as carbon nanotubes (CNT) within the pores of the zeolite structure. The growth of CNT is achieved within the porous structure of the zeolite crystals whereby the pores can be defined as confined spaces (channels) in nanometer dimensions acting as a micro-reactor for CNT growth.

Abstract: Methods are provided for obtaining soluble or insoluble poly(iptycenylene vinylene) homo- and co-polymers via a soluble precursor polymer. The polymers obtained by the methods can be used in electronic or opto-electronic devices, e.g., chemosensors.

Abstract: A method of manufacturing a semiconductor device having damascene structures with air gaps is provided. In one embodiment, the method comprises providing a substantially planar layer having a first metal layer, depositing a via level dielectric layer, patterning the via level dielectric layer, at least partly etching the via level dielectric layer, depositing a disposable layer on the at least partly etched via level dielectric layer, patterning the disposable layer, depositing a second metal layer, planarizing second metal layer, depositing permeable dielectric layer after planarizing the second metal layer, and removing the disposable layer through the permeable dielectric layer to form air gaps.

Abstract: The present invention is related to a method and apparatus for cleaning a semiconductor substrate including on a surface of the substrate at least one structure comprising a first conducting or semiconducting material, surrounded by a layer of a second conducting or semiconducting material, said layer essentially extending over the totality of said surface, the first and second material being in physical contact, the method comprising the steps of: providing the substrate, positioning a counter-electrode facing the substrate surface, and supplying an electrolytic fluid to the space between the surface and the electrode, the counter-electrode acting as an anode in the galvanic cell defined by the substrate surface, the cleaning fluid and the counter-electrode.

Abstract: A system and method for converting on a computer environment a first code into a second code to improve performance or lower energy consumption on a targeted programmable platform is disclosed. The codes represent an application. In one aspect, the method includes loading on the computer environment the first code and for at least part of the variables within the code the bit width required to have the precision and overflow behavior as demanded by the application. The method further includes converting the first code into the second code by grouping operations of the same type on the variables for joint execution on a functional unit of the targeted programmable platform, the grouping operations using the required bit width, wherein the functional unit supports one or more bit widths, the grouping operation being selected to use at least partially one of the supported bit widths.

Abstract: One inventive aspect relates to a reconfigurable cavity resonator. The resonator comprises a cavity delimited by metallic walls. The resonator further comprises a coupling device for coupling an electromagnetic wave into the cavity. The resonator further comprises a tuning element for tuning a resonance frequency at which the electromagnetic wave resonates in the cavity. The tuning element comprises one or more movable micro-electromechanical elements with an associated actuation element located in their vicinity for actuating each of them between an up state and a down state. The movable micro-electromechanical elements at least partially have a conductive surface and are mounted within the cavity.

Abstract: One inventive aspect is related to a method of bonding two elements and micro-electronic devices produced according to such methods. In one aspect, a micro-electronic device includes a first and a second element, bonded together by a joining structure. The joining structure has a first micropattern portion, a second micropattern portion, and a joining portion in between the first and second micropattern portions. The first and second micropattern portions are made of cobalt. The joining portion includes intermetallic compounds of cobalt and tin (Sn).

Abstract: Interdigitated electrode arrays are very promising devices for multi-parameter (bio)sensing, for example the label-free detection of nucleic acid hybridisation for diagnostic applications. The current disclosure provides an innovative method for the affordable manufacturing of polymer-based arrays of interdigitated electrodes with ?m-dimensions. The method is based on a combination of an appropriate three-dimensional structure and a single and directional deposition of conductive material. The three-dimensional structure can be realized in a polymer material using a moulding step, for which the moulds are manufactured by electroplating as a reverse copy of a silicon master structure. In order to ensure sufficient electrical isolation and individual, but convenient, accessibility of the sensors in the array, the interdigitated electrode regions need to be complemented with specific features on the three-dimensional structure. Combined with the use of e.g.

Abstract: Devices and methods for junction formation in manufacturing a semiconductor device are disclosed. The devices have shallow junction depths far removed from end-of range defects. The method comprises forming an amorphous region in a crystalline semiconductor such as silicon down to a first depth, followed by implantation of a substitutional element such as carbon to a smaller depth than the first depth. The region is then doped with suitable dopants, e.g. phosphorus or boron, and the amorphous layer recrystallized by a thermal process.

Abstract: A method and system for setting up multiple patterning lithographic processing of a pattern in a single layer is disclosed. The multiple patterning lithographic processing comprises a first and second patterning step. In one aspect, a method includes, for at least one process condition, obtaining values for a metric expressing a splitting correlated process quality as function of design parameters of a pattern and/or split parameters for the multiple patterning lithographic processing. The method also includes evaluating the values of the metric and selecting based thereon design and split parameters considering the process condition. The method may further include deriving design and/or split guidelines for splitting patterns to be processed using multiple patterning lithographic processing based on the evaluation.

Abstract: The present invention provides an etching solution for revealing defects in a germanium layer, a method for revealing defects in a germanium layer using such an etching solution and to a method for making such an etching solution. The etching solution according to embodiments of the present invention is able to exhibit an etch rate of between 4 nm·min?1 and 450 nm·min?1, which makes it suitable to be used for revealing defects in a thin layer of germanium, i.e. in a layer of germanium with a thickness of between 20 nm and 10 ?m, for example between 20 nm and 2 ?m, between 20 nm and 1 ?m or between 20 nm and 200 nm.

Abstract: Photoelectrochemical cells and methods are provided, in particular, to the functionalization of semiconductor surfaces such that its semiconducting and light generating properties are maintained and the surface becomes stable in wet environments. In particular the preferred embodiments relate to unstable semiconductor materials which have photocurrent generating properties, and to methods for the functionalization of surfaces with metallic carbon nanotubes (CNTs).