Abstract: A method of fabricating a multi-gate device is disclosed. In one aspect, the method includes providing a substrate having a first semiconductor layer with a first carrier mobility enhancing parameter, an insulating layer, a second semiconductor layer with a second carrier mobility enhancing parameter different from the first carrier mobility enhancing parameter. A first and second dielectric layer are then provided on the substrate. A first trench is formed in a first active region through the dielectric layers, the second semiconductor layer and the buried insulating layer. A first fin is formed in the first trench, protruding above the first dielectric layer and having the first carrier mobility enhancing parameter. A second trench is formed in a second active region through the dielectric layers. A second fin is formed in the second trench, protruding above the first dielectric layer and having the second mobility enhancing parameter.

Abstract: Methods, apparatus and software products are described for design-time data-assignment techniques for hierarchical memories, e.g., multi-banked memories in an essentially digital system as well as methods, apparatus and software products for run-time memory management techniques of such a system. Memory assignment techniques are described for assigning data to a hierarchical memory particularly for multi-tasked applications where data of dynamically created/deleted tasks is allocated at run-time. The energy consumption of hierarchical memories such as multi-banked memories depends largely on how data is assigned to the memory banks. Methods, apparatus and software products are described for design-time data-assignment techniques for hierarchical memories, e.g., multi-banked memories in an essentially digital system which improve a cost function such as energy consumption.

Abstract: The present disclosure is related to non-volatile memory devices comprising a reversible resistivity-switching layer used for storing data. The resistivity of this layer can be varied between at least two stable resistivity states such that at least one bit can be stored therein. In particular this resistivity-switching layer is a metal oxide or a metal nitride. A resistivity-switching non-volatile memory element includes a resistivity-switching metal-oxide layer sandwiched between a top electrode and a bottom electrode. The resistivity-switching metal-oxide layer has a gradient of oxygen over its thickness. The gradient is formed in a thermal oxidation step. Set and reset voltages can be tuned by using different oxygen gradients.

Abstract: The present invention recites a new method for manufacturing Group III-N field-effect devices, such as HEMT, MOSHFET, MISHFET devices or MESFET devices, grown by Metal-Organic Vapor Phase Expitaxy, with higher performance (power), by covering the surface with a thin SiN layer on the top AlGaN layer, in the reactor where the growth takes place at high temperature, prior cooling down the structure and loading the sample out of the reactor, as well as a method to produce some HEMT transistors on those heterostructures, by depositing the contact on the surface without any removal of the SiN layer by MOCVD. The present invention recites also a device.

Abstract: One inventive aspect is related to a method of bonding two elements. The method comprises producing on a first element a first micropattern, comprising a first metal layer. The method further comprises producing on a second element a second micropattern, comprising a second metal layer. The method further comprises applying onto the first micropattern and/or on the second micropattern a layer of solder material. The method further comprises producing on at least one of the elements a patterned non-conductive adhesive layer around the micropattern on the element. The method further comprises joining the first micropattern and the second micropattern by means of a thermocompression or reflow method, wherein the producing of an adhesive layer is performed before the joining such that the first and second elements are secured to each other by the adhesive layer(s) after joining.

Abstract: One inventive aspect is related to an atomic force microscopy probe. The probe comprises a tip configuration with two probe tips on one cantilever arm. The probe tips are electrically isolated from each other and of approximately the same height with respect to the cantilever arm. The outer surface of the tip configuration has the shape of a body with a base plane and an apex. The body is divided into two sub-parts by a gap located approximately symmetrically with respect to the apex and approximately perpendicular to the base plane. Another inventive aspect related to methods for producing such an AFM probe.

Abstract: The disclosed systems and methods relate to floating gate non-volatile memory cells, with a floating gate comprising at least two layers constructed in different conductive or semiconductive materials.

Abstract: A method for determining programming/erase conditions and a method for operating a charge-trapping semiconductor device are disclosed. Programming and erase conditions are determined such that a first net charge distribution variation profile, upon going from programmed to erased state, is substantially the opposite of a second net charge distribution variation profile, upon going from erased to programmed state.

Abstract: A method of forming a quantum system comprising computational elements, consisting of an insulated ring of superconductive material, and semi-closed rings, which are used as an interface or input/output facility between the quantum bit and the external world, is disclosed. Faraday induction is used to provide electromagnetic coupling between adjacent computational elements and between the computational elements with interface elements of the quantum system. Therefore the corresponding magnetic flux acts as an information carrier. Ferromagnetic cores are used to improve the magnetic coupling between adjacent elements of the quantum system.

Abstract: A non-volatile memory device having a control gate on top of the second dielectric (interpoly or blocking dielectric), at least a bottom layer of the control gate in contact with the second dielectric being constructed in a material having a predefined high work-function and showing a tendency to reduce its work-function when in contact with a group of certain high-k materials after full device fabrication. At least a top layer of the second dielectric, separating the bottom layer of the control gate from the rest of the second dielectric, is constructed in a predetermined high-k material, chosen outside the group for avoiding a reduction in the work-function of the material of the bottom layer of the control gate. In the manufacturing method, the top layer is created in the second dielectric before applying the control gate.

Abstract: A method is provided for forming a capping layer comprising Cu, N, and also Si and/or Ge onto a copper conductive structure, said method comprising the sequential steps of: forming, at a temperature range between 200° C. up to 400° C., at least one capping layer onto said copper conductive structure by exposing said structure to a GeH4 and/or a SiH4 comprising ambient, performing a NH3 plasma treatment thereby forming an at least partly nitrided capping layer, forming a dielectric barrier layer onto said at least partly nitrided capping layer, wherein prior to said step of forming said at least one capping layer a pre-annealing step of said copper conductive structure is performed at a temperature range between 250° C. up to 450° C.

Abstract: The invention relates to a method for determining a set of programming conditions for a given type of charge-trapping non-volatile memory device, comprising the steps of: (a) selecting different sets of programming parameters to be applied to the corresponding number of non-volatile memory devices of said type, (b) programming said number of non-volatile memory devices by means of the sets of programming parameters, (c) determining an actual spatial charge distribution of the charge trapping layer of each of the programmed devices, (d) determining the influence of at least one of the programming parameters on the spatial charge distribution, (e) determining an optimised value for at least one of the programming parameters, (f) entering each optimised value in said sets of programming parameters and repeating steps b) to e) at least once.

Abstract: A method for forming at least one quantum dot at least one predetermined location on a substrate is disclosed. In one aspect, the method comprises providing a layer of semiconductor material on an insulating layer on the substrate. The layer of semiconductor material is patterned so as to provide at least one line of semiconductor material having a width (wL) and having a local width variation at least one predetermined location where the at least one quantum dot has to be formed. The local width variation has an amplitude (A) of between about 20 nm and 35 nm higher than the width wL of the at least one line. The at least one line is patterned to form at least one quantum dot. A design for a lithographic mask for use with the method and a method for making such a design are also disclosed.

Abstract: A method of manufacturing a dual work function semiconductor device is disclosed. In one aspect, the method comprises providing a first metal layer over a first electrode in a first region, and at least a first work function tuning element. The method further comprises providing a second metal layer of a second metal in a second region at least over a second electrode. The method further comprises performing a first silicidation of the first electrode and a second silicidation of the second electrode simultaneously.

Abstract: A method for forming catalyst nanoparticles on a substrate and a method for forming elongate nanostructures on a substrate using the nanoparticles as a catalyst are provided. The methods may advantageously be used in, for example, semiconductor processing. The methods are scalable and fully compatible with existing semiconductor processing technology. Furthermore, the methods allow forming catalyst particles and elongate nanostructures at predetermined locations on a substrate.

Abstract: A method of managing the operation of a system is presented. The system includes a processing subsystem configured to run a multimedia application and a telecommunication subsystem. The method includes determining telecom environment conditions, and selecting a configuration from a plurality of configurations. The selecting is based at least in part on the determined environmental conditions. The method also includes setting control parameters such as channel speed in the multimedia application and/or the telecommunication subsystem to cause the system to operate at the selected configuration, and operating the system at the selected configuration. The configuration are determined by simultaneously updating control parameters by a controller of both the multimedia application and the telecommunication subsystem.

Abstract: The present disclosure relates to methods for forming a high-k gate dielectric, the methods comprising the steps of providing a semiconductor substrate, cleaning the substrate, performing a thermal treatment, and performing a high-k dielectric material deposition, wherein said thermal treatment step is performed in a non-oxidizing ambient, leading to the formation of a thin interfacial layer between said semiconductor substrate and said high-k dielectric material and wherein the thickness of said thin interfacial layer is less than 10 ?.

Abstract: A method is provided for characterizing an immersion lithography process of a device using an immersion liquid. In order to study pre-soak and post-soak effects on the image performance of an immersion lithography process, the method includes determining at least one image performance characteristic as function of contact times between the immersion liquid and the device for a device illuminated in a dry lithography process and contacted with said immersion liquid prior and/or after said illumination. Based on the image performance characteristic, a lithography process characteristic is derived for the immersion lithography process.

Abstract: A method and apparatus for removing a first liquid from a surface of a substrate is provided. A second liquid is supplied to at least part of a surface of a substrate having a rotary movement. The rotary movement has a center of rotation and an edge of rotation. The second liquid is directed from the center of rotation to the edge of rotation using a nozzle. A dry zone is created on the substrate as the position of the spray moves from the center of rotation to the edge of rotation. As a result, the first liquid and the second liquid are removed from the surface of the substrate.

Abstract: A method for optimizing a design for a device is disclosed. Such an optimization is performed with respect to a predetermined metric, e.g. device speed, area, power consumption or yield. In one aspect, the method comprises obtaining a design for a device. The design comprises design components. The method also comprises determining from the design components at least one group of first design components that has a higher sensitivity to the predetermined metric than second design components. The first design components may be on the critical path in the design. The method further comprises tuning the first design components and the technology for manufacturing the first design components thus reducing the variability of the first design components and obtaining an optimized design with respect to the predetermined metric.