Patents Assigned to InterUniversitaire Microelektronica
-
Patent number: 6721141Abstract: The present invention concerns in a first aspect a spin-valve structure having a first and a second free ferromagnetic layer and a spacer layer positioned between the first and second free ferromagnetic layer, and wherein the first free ferromagnetic layer is positioned on a substrate. In a preferred embodiment of the invention, the first free ferromagnetic layer is in direct contact with the surface of the substrate.Type: GrantFiled: July 9, 1999Date of Patent: April 13, 2004Assignees: Interuniversitair Microelektronica Centrum (IMECVZW), Katholieke Universiteit Leuven Research & DevelopmentInventors: Karen Attenborough, Hans Boeve, Jo De Boeck, Jean-Pierre Celis
-
Publication number: 20040063326Abstract: A method of etching a semiconductor substrate is described, the method comprising the steps of applying a paste containing an etchant to the substrate, and carrying out a thermal processing step to etch a part or a layer of the substrate where the paste has been applied. The etchant paste is preferably a caustic etching paste. The etchant paste may be applied selectively to a major surface of the substrate to form a pattern of applied paste. For example, the paste may be applied by a printing method, such as screen-printing. The method may be used to produce solar cells.Type: ApplicationFiled: June 27, 2003Publication date: April 1, 2004Applicant: Interuniversitair Microelektronica Centrum (IMEC)Inventors: Jozef Szlufcik, Emmanuel Van Kerschaver, Christophe Allebe
-
Patent number: 6711813Abstract: Method and apparatus of fabricating a core laminate Printed Circuit Board structure with highly planar external surfaces is provided. A pre-formed flat material including a first resinous sub-material and a second carrier sub-material is used to planarize external surfaces. During lamination, uniform pressure is applied to the pre-formed flat sheet which covers the upper surface of the printed circuit. The resinous material of the first sub-material flows to fill the crevices, vias, etc. of the upper surface of the PCB. Moreover, due to the uniform pressure on the pre-formed flat sheet, the resinous first sub-material is planarized. This planarized surface provides a suitable base substrate for a thin film multilayer build-up structure and that provides electrical connections between the thin film top layers and the Printed Circuit Board—style core layers.Type: GrantFiled: November 6, 2000Date of Patent: March 30, 2004Assignee: Interuniversitair Microelektronica CentrumInventors: Eric Beyne, Francois Lechleiter
-
Patent number: 6707121Abstract: Structures and methods are disclosed to produce mechanical strength in Micro Electro Mechanical Systems by increasing the moment of inertia of some of the composing elements. In one aspect, a thermal sensor with improved mechanical strength, thermal insulation and time constant is achieved. Moreover, the current method and apparatus is advantageous in terms of process time and process cost, particularly in the area of lithographic patterning.Type: GrantFiled: March 23, 2001Date of Patent: March 16, 2004Assignee: Interuniversitair Microelektronica Centrum (IMEC VZW)Inventors: Piet De Moor, Chris Van Hoof
-
Patent number: 6707110Abstract: Electrostatic discharge protection device comprising a first highly p-doped region with a base contact, a first highly n-doped region with a collector contact, a second highly n-doped region with an emitter contact and located between the first highly p-doped region and the second highly n-doped region, the first highly p-doped region and the second highly n-doped region being applied in a weakly p-doped region which a has a lateral overlap extending towards the first highly n-doped region, the lateral overlap having a width, the first highly n-doped region being applied in a weakly n-doped region, the weakly p-doped region and the weakly n-doped region being applied in a more weakly n-doped region, and a highly n-doped buried layer located underneath the more weakly n-doped region and extending below at least a portion of the weakly n-doped region and at least a portion of the weakly p-doped region.Type: GrantFiled: April 25, 2002Date of Patent: March 16, 2004Assignees: Interuniversitair Microelektronica Centrum, Alcatel SAInventors: Vincent De Heyn, Guido Groeseneken, Louis Vacaresse, Geert Gallopyn, Hugo Van Hove
-
Publication number: 20040028952Abstract: Dielectric material compositions comprising HfO2 and a second compound are disclosed. The compositions are characterized by at least a part of the compositions being in a cubic crystallographic phase. Further, semiconductor based devices comprising such dielectric material compound and method for forming such compounds are disclosed.Type: ApplicationFiled: June 10, 2003Publication date: February 12, 2004Applicant: Interuniversitair Microelektronica Centrum (IMEC vzw)Inventors: Eduard Cartier, Jerry Chen, Chao Zhao
-
Patent number: 6690008Abstract: An atomic force microscopy (AFM) probe and a method of manufacturing mounted probes for AFM applications. The method implements an optimized soldering procedure for mounting a probe to a holder chip. In one embodiment, a metallisation system of Ti:W+Ni+Au is applied with a SnBi58 solder paste in combination with a hotplate. The mechanical connection between the probe and holder chip is preferably rigid. The soldered probe is highly conductive and the probe-holder chip assembly shows clear resonance peaks in tapping mode AFM.Type: GrantFiled: September 14, 2001Date of Patent: February 10, 2004Assignee: Interuniversitair Microelektronica Centrum (IMEC)Inventors: Thomas Hantschel, Wilfried Vandervorst
-
Publication number: 20040018532Abstract: The present invention is related to a device suitable for the preparation of a sensor, comprising a substrate comprising a metal layer, the metal layer comprising at least a first region wherein to a first region is attached a first species comprising a compound of chemical formula:Type: ApplicationFiled: June 3, 2003Publication date: January 29, 2004Applicant: Interuniversitair Microelektronica Centrum (IMEC)Inventor: Filip Frederix
-
Patent number: 6681069Abstract: A waveguide component has a slab waveguide, a rib waveguide, and a mode transition section where the rib waveguide and the slab waveguide are adjacent, and where the rib waveguide is tapered, to provide optical coupling, and lateral confinement rib waveguides are provided along the slab waveguide in the mode transition section to confine light from spreading laterally. The lateral confinement ribs can be formed in the same step with the same mask as used for the taper, to ensure alignment with the taper. They can be arranged either side of the taper. The lateral confinement ribs are significant for enabling a mode transition section which couples with low loss. In particular, it reduces the need for the taper to be so fine, or the taper to be made in both vertical and horizontal axes, both of which cause fabrication difficulties.Type: GrantFiled: March 29, 2002Date of Patent: January 20, 2004Assignees: Interuniversitair Microelektronica Centrum, Universidad Publica de Navarra, Universiteit GentInventors: Marko Galarza, Kurt De Mesel, Candido Aramburu, Roel Baets
-
Patent number: 6678844Abstract: A method for estimating the BER for telecommunication systems, particular those characterized by signals having high crest factors or causing large inband nonlinear distortions. The set of signals used by the system is divided into subsets according to a characteristic such as signal crest factor, and a BER estimation method is chosen for each subset. Signals causing a large BER are simulated more efficiently using a Monte Carlo simulation, while low BER estimations more efficiently use a quasi-analytical method. The method results in improved accuracy because the noise contribution in quasi-analytical methods can be better approximated for signals having a small crest factor range, and drastically reduces the number of experiments, measurements or simulations which are needed to obtain an accurate BER estimation, as compared to standard Monte Carlo techniques.Type: GrantFiled: December 22, 2000Date of Patent: January 13, 2004Assignee: Interuniversitair Microelektronica Centrum (IMEC)Inventors: Gerd Vandersteen, Jozef Verbeeck, Yves Rolain, Johan Schoukens, Pierre Wambacq, Stephane Donnay
-
Patent number: 6678473Abstract: The present invention provides a cross-connect switching device and a method of cross-connect switching of Nf * N1 channels to one of a plurality of output lines of the switching device, Nf * N1 being equal or greater than four. The device and method includes three basic elements: 1) a partial demultiplexer for partially demultiplexing the channels on its input lines into groups of channels and individual channels; 2) a space switch for switching groups of channels en bloc; and 3) a combiner unit for combining individual channels onto one of the output lines of the cross-connect switching device. The cross-connect switching device according to the present invention may be combined with similar or dissimilar switching devices to form a larger switching device.Type: GrantFiled: December 15, 1999Date of Patent: January 13, 2004Assignees: Interuniversitair Microelektronica Centrum (IMEC), RIJSUniversiteit GentInventor: Geert Morthier
-
Patent number: 6676765Abstract: The present invention is related to a method of removing particles and a liquid from a surface of a substrate using at least one rotating cleaning pad. The approach, according to the present invention, is a technique wherein a sharp liquid-vapor boundary is created on the surface of the substrate adjacent to the last wetted rotating cleaning pad of a plurality of rotating cleaning pads and particularly between this last wetted rotating cleaning pad and a first edge of the substrate.Type: GrantFiled: May 21, 2001Date of Patent: January 13, 2004Assignee: Interuniversitair Microelektronica CentrumInventors: Paul Mertens, Mark Meuris, Marc Heyns
-
Publication number: 20030235370Abstract: An optical waveguide to fiber coupler comprises a substrate, a first waveguide and a second waveguide. The first and second waveguides are formed on the substrate and intersect at a right angle. A diffraction grating structure is formed at the intersection of the first and second waveguides, such that, when the coupler is physically abutted with a single mode optical fiber, in operation, a polarization split is obtained that couples orthogonal modes from the single-mode optical fiber into single identical modes in the first and second waveguides. Also, employing the coupler in optical polarization diverse applications provides for implementing a polarization insensitive photonic integrated circuit using such diffraction grating structures, such as, for example, photonic crystals.Type: ApplicationFiled: April 10, 2003Publication date: December 25, 2003Applicants: Interuniversitair Microelektronica Centrum (IMEC vzw), Universiteit GentInventors: Dirk Taillaert, Roel Baets
-
Patent number: 6665849Abstract: In order to design on-chip interconnect structures in a flexible way, a CAD approach is advocated in three dimensions, describing high frequency effects such as current redistribution due to the skin-effect or eddy currents and the occurrence of slow-wave modes. The electromagnetic environment is described by a scalar electric potential and a magnetic vector potential. These potentials are not uniquely defined, and in order to obtain a consistent discretization scheme, a gauge-transformation field is introduced. The displacement current is taken into account to describe current redistribution and a small-signal analysis solution scheme is proposed based upon existing techniques for static fields in semiconductors. In addition methods and apparatus for refining the mesh used for numerical analysis is described.Type: GrantFiled: June 25, 2001Date of Patent: December 16, 2003Assignee: Interuniversitair Microelektronica Centrum vzwInventors: Peter Meuris, Wim Schoenmaker, Wim Magnus
-
Patent number: 6662631Abstract: A method and apparatus for evaluation of films, such as low-k thin films with nano-scale pores, are provided. The evaluation may include characterization of the pore structure, the characterization results in determining pore sizes, hence obtaining pore size data. Moreover, the characterization may result in a non-destructive evaluation of mechanical properties, in particular the Young's Modulus, or the effect of interfering physical & chemical factors such as Pore Killers. Further, in line monitoring or studying of pore structure porosity and pore size distribution (PSD) of low-k films and evaluation of the mechanical properties of porous low-k films simultaneously using the same set of experimental data is provided.Type: GrantFiled: July 12, 2002Date of Patent: December 16, 2003Assignees: Interuniversitair Microelektronica Centrum, Technokom-Centre Advanced Technology, XPEQTInventors: Mikhail Rodionovich Baklanov, Konstantin Petrovich Mogilnikov, Karen Maex, Denis Shamiryan, Fedor Nikolaevich Dultsev
-
Patent number: 6664192Abstract: Methods are disclosed for selective deposition on desired materials. In particular, barrier materials are selectively formed on insulating surfaces, as compared to conductive surfaces. In the context of contact formation and trench fill, particularly damascene and dual damascene metallization, the method advantageously lines insulating surfaces with a barrier material. The selective formation allows the deposition to be “bottomless,” thus leaving the conductive material at a via bottom exposed for direct metal-to-metal contact when further conductive material is deposited into the opening after barrier formation on the insulating surfaces. Desirably, the selective deposition is accomplished by atomic layer deposition (ALD), resulting in highly conformal coverage of the insulating sidewalls in the opening.Type: GrantFiled: April 15, 2002Date of Patent: December 16, 2003Assignees: Interuniversitair Microelektronica Centrum (IMEC), ASM International N.V.Inventors: Alessandra Satta, Karen Maex, Kai-Erik Elers, Ville Antero Saanila, Pekka Juha Soininen, Suvi P. Haukka
-
Patent number: 6663915Abstract: The present invention describes a method for copper deposition on a substrate having a barrier layer wherein a substrate (2) and an activator (1) are immersed in a copper plating bath in order to contact each other for a predetermined period.Type: GrantFiled: November 13, 2001Date of Patent: December 16, 2003Assignee: Interuniversitair Microelektronica CentrumInventors: Roger Palmans, Yuri Lantasov
-
Patent number: 6653682Abstract: Apparatus for an electrically programmable and erasable memory device and methods for programming, erasing and reading the device. The device has a single transistor including a source, a drain, a control gate and a floating gate positioned between the control gate, the source and the drain, where the floating gate is capacitively coupled to the drain. At least one part of the floating gate is partly positioned between the control gate, the drain and the source, and the other part of the floating gate overlaps with the drain. Further, the single transistor of the device includes means for injecting hot electrons generated by the drain induced secondary impact ionization onto the floating gate. Additionally, the means are arranged to induce Fowler-Nordheim tunnelling of charges from the floating gate to the drain.Type: GrantFiled: October 25, 2000Date of Patent: November 25, 2003Assignee: Interuniversitair Microelektronica Centrum (IMEL,VZW)Inventors: Jan Van Houdt, Gang Xue
-
Patent number: 6649485Abstract: A method for the manufacture, formation, and removal of porous layers in a semiconductor substrate having at least a surface acting as a cathode. The method comprises applying a solution comprising negative Fluorine (F−) ions between the surface of the semiconductor substrate and an anode. The method further comprises applying a predetermined current between the anode and the cathode. The method further comprises maintaining the predetermined current at substantially the same current value for a sufficient amount of time to obtain a low porosity layer at said surface. A high porosity layer positioned under the low porosity layer is also obtained by the method of the invention.Type: GrantFiled: March 9, 2001Date of Patent: November 18, 2003Assignee: Interuniversitair Microelektronica Centrum (IMEC)Inventors: Chetan Singh Solanki, Renat Bilyalov, Jef Poortmans, Guy Beaucarne
-
Publication number: 20030209754Abstract: A planar high-density EEPROM split gate memory structure, is formed using two poly-layers and chemical-mechanical-polishing processes. Stripes of contiguous poly lines, alternately formed in one of the two poly-layers, constitute the memory structure. Source and drain regions are formed self-aligned to the outer borders of this memory structure. Depending on the biasing scheme a poly line is used as the select gate of the memory cell while an adjacent poly line is used as program gate, so to have charge stored underneath this adjacent poly line using source-side-injection of charge carriers. The other poly lines are biased to form conductive channels between the select and program gate to the source and drain regions. These conductive channels form soft source and drain regions next to the select and program gate in use.Type: ApplicationFiled: April 25, 2003Publication date: November 13, 2003Applicant: Interuniversitair Microelektronica Centrum (IMEC)Inventor: Luc Haspeslagh