Abstract: The present invention relates to a method for selectively removing a high-k material comprising providing a high-k material on a semiconductor substrate, and contacting the high-k material with a solution comprising HF, an organic compound, and an inorganic acid.
Type:
Grant
Filed:
March 9, 2004
Date of Patent:
November 7, 2006
Assignee:
Interuniversitair Microelektronica Centrum (IMEC)
Abstract: In order to design on-chip interconnect structures in a flexible way, a CAD approach is advocated in three dimensions, describing high frequency effects such as current redistribution due to the skin-effect or eddy currents and the occurrence of slow-wave modes. The electromagnetic environment is described by a scalar electric potential and a magnetic vector potential. These potentials are not uniquely defined, and in order to obtain a consistent discretization scheme, a gauge-transformation field is introduced. The displacement current is taken into account to describe current redistribution and a small-signal analysis solution scheme is proposed based upon existing techniques for static fields in semiconductors. In addition methods and apparatus for refining the mesh used for numerical analysis is described.
Type:
Grant
Filed:
July 29, 2003
Date of Patent:
October 17, 2006
Assignee:
Interuniversitair Microelektronica Centrum vzw
Inventors:
Peter Meuris, Wim Schoenmaker, Wim Magnus
Abstract: A method of producing a semiconductor device on a silicon on insulator (SOI) substrate is disclosed. In one aspect, the method comprises providing a device with a monocrystalline semiconductor layer on an insulating layer; providing a mask on the semiconductor layer to provide first shielded portions and first unshielded portions, amorphizing the first unshielded portions to yield first amorphized portions of the monocrystalline semiconductor layer, implanting a first dopant in the first amorphized portions, applying a first solid phase epitaxial regrowth action to the semiconductor device while using the first shielded portions as monocrystalline seeds.
Type:
Grant
Filed:
March 15, 2005
Date of Patent:
October 17, 2006
Assignees:
Interuniversitair Microelektronica Centrum (IMEC) vzw, Koninklijke Philips Electronics
Abstract: A method for designing an electronic system having at least one digital part. The method includes representing a behavioral description of the system as a first set of objects with a first set of relations therebetween. Furthermore, the method includes refining said behavioral description into an implementable description of said system, said implementable description being represented as a second set of objects with a second set of relations therebetween. Also, the method includes retaining at least one of said second objects for reuse in the design of a second electronic system.
Type:
Grant
Filed:
March 19, 1999
Date of Patent:
September 26, 2006
Assignee:
Interuniversitair Microelektronica Centrum (IMEC)
Inventors:
Patrick Schaumont, Radim Cmar, Serge Vernalde
Abstract: The present invention is related to a method of producing a semiconductor device and the resulting device. The method is suitable in the first place for producing high power devices, such as High Electron Mobility Transistors (HEMT), in particular HEMT-devices with multiples source-gate-drain groups or multiple base bipolar transistors. According to the method, the interconnect between the source contacts is not produced by air bridge structures, but by etching vias through the semiconductor layer directly to the ohmic contacts and applying a contact layer on the backside of the device.
Type:
Application
Filed:
January 30, 2006
Publication date:
September 14, 2006
Applicant:
Interuniversitair Microelektronica Centrum (IMEC)
Abstract: A method for the production of airgaps in a semiconductor device and device produced therefrom. The formation of airgaps is accomplished, in part, by chemically and/or mechanically changing the properties of a first dielectric layer locally, such that at least part of said first dielectric layer is converted locally and becomes etchable by a first etching substance. The local conversion of the dielectric material may be achieved during anisotropic etching of the material in oxygen containing plasma or ex-situ by performing an oxidizing step (e.g., a UV/ozone treatment or supercritical carbon dioxide with addition of an oxidizer). Formation of airgaps is achieved after creation of conductive lines and, alternatively, a barrier layer by a first etching substance. The airgaps are formed in a dual damascene structure, near the vias and/or the trenches of the damascene structure.
Type:
Application
Filed:
March 22, 2006
Publication date:
August 10, 2006
Applicants:
Interuniversitair Microelektronica Centrum (IMEC vzw), Texas Instruments, Inc.
Inventors:
Gerald Beyer, Jean Paul Mussy, Karen Maex, Victor Sutcliffe
Abstract: Non-volatile memory devices are disclosed. In a first example non-volatile memory device, programming and erasing of the memory device is performed through the same insulating barrier without the use of a complex symmetrical structure. In the example device, programming is accomplished by tunneling negative charge carriers from a charge supply region to a charge storage region. Further in the example device, erasing is accomplished by tunneling positive carriers from the charge supply region to the charge storage region. In a second example non-volatile memory device, a charge storage region with spatially distributed charge storage region is included. Such a charge storage region may be implemented in the first example memory device or may be implemented in other memory devices. In the second example device, programming is accomplished by tunneling negative charge carriers from a charge supply region to the charge storage region.
Type:
Application
Filed:
March 2, 2006
Publication date:
August 10, 2006
Applicant:
Interuniversitair Microelektronica Centrum (IMEC vzw)
Abstract: A method is described for designing a micro electromechanical device in which the risk of self-actuation of the device in use is reduced. The method includes locating a first conductor in a plane and locating a second conductor with its collapsible portion at a predetermined distance above the plane. The method also includes laterally offsetting the first conductor by a predetermined distance from a region of maximum actuation liability. The region of maximum actuation liability is where an attraction force to be applied to activate the device is at a minimum.
Type:
Application
Filed:
December 23, 2005
Publication date:
August 3, 2006
Applicant:
Interuniversitair Microelektronica Centrum (IMEC)
Abstract: A method of depositing a structural SiGe layer is presented. The structural SiGe layer may be located on top of a sacrificial layer above a substrate. The substrate may contain a semiconductor device such as a CMOS electronic circuit. The presented method uses a silicon source and a germanium source in a reaction zone to grow the structural SiGe layer. Hydrogen is introduced into the reaction zone and it may be used to dilute the silicon source and the germanium source. The resultant reaction occurs at temperatures below 450 degrees C, thereby preventing degradation of electronic device and/or other devices/materials located in the substrate.
Type:
Application
Filed:
January 24, 2006
Publication date:
July 27, 2006
Applicant:
Interuniversitair Microelektronica Centrum (IMEC)
Inventors:
Ann Witvrouw, Maria Gromova, Marc Schaekers, Serge Vanhaelemeersch, Brenda Eyckens
Abstract: Damascene stacks for use in semiconductor devices and methods for making such stacks are disclosed. An example damascene stack includes a substantially planar lower liner layer and a patterned sacrificial dielectric layer disposed on top of the lower liner layer, where the patterned sacrificial dielectric layer includes an interconnect structure of the damascene stack. The example damascene stack further includes a substantially planar upper liner layer disposed on top of the patterned sacrificial dielectric layer, where the upper liner layer being formed of a material that is resistant to etching by a first etch compound. There is at least one plug-hole in the upper liner layer, where the at least one plug-hole is (i) adjacent to the interconnect structure and (ii) formed by locally converting a portion of the upper liner layer to be etchable by the first etch compound and removing the locally converted portion of the upper liner layer using the first etch compound.
Type:
Application
Filed:
March 16, 2006
Publication date:
July 20, 2006
Applicant:
Interuniversitair Microelektronica Centrum (IMEC vzw)
Inventors:
Jean Gueneau de Mussy, Gerald Beyer, Karen Maex
Abstract: A method for the production of airgaps in a semiconductor device and device produced therefrom. The formation of airgaps is accomplished, in part, by chemically and/or mechanically changing the properties of a first dielectric layer locally, such that at least part of said first dielectric layer is converted locally and becomes etchable by a first etching substance. The local conversion of the dielectric material may be achieved during anisotropic etching of the material in oxygen containing plasma or ex-situ by performing an oxidizing step (e.g., a UV/ozone treatment or supercritical carbon dioxide with addition of an oxidizer). Formation of airgaps is achieved after creation of conductive lines and, alternatively, a barrier layer by a first etching substance. The airgaps are formed in a dual damascene structure, near the vias and/or the trenches of the damascene structure.
Type:
Grant
Filed:
September 30, 2004
Date of Patent:
July 18, 2006
Assignees:
Interuniversitair Microelektronica Centrum (IMEC vzw), Texas Instruments, Inc.
Inventors:
Gerald Beyer, Jean Paul Gueneau de Mussy, Karen Maex, Victor Sutcliffe
Abstract: A method of controlling an internal stress in a polycrystalline silicon-germanium layer deposited on a substrate. The method includes selecting a deposition pressure that is at or below atmospheric pressure and selecting a deposition temperature that is no greater than 700° C. The deposition pressure and the deposition temperature are selected so as to achieve an internal stress in the silicon-germanium layer that is within a predetermined range.
Type:
Grant
Filed:
August 17, 2004
Date of Patent:
July 11, 2006
Assignee:
Interuniversitair Microelektronica Centrum (IMEC vzw)
Inventors:
Paolo Fiorini, Sherif Sedky, Matty Caymax, Christiaan Baert
Abstract: A method and magnetic device for improving the desirable properties of a magnetic device, e.g., magnetization uniformity and reproducibility. Moreover the invention provides magnetic cells that are more magnetically homogeneous, with smaller amount of end domain magnetization canting from the average cell magnetization direction. The invention may provide a magnetic memory cell with less variation in switching fields, more spatially coherent dynamical magnetic properties for high speed and processional or coherent magnetic switching, and higher signal due to the increased uniformity. It may provide a magnetic sensor with more spatially coherent magnetic properties for high speed and processional or coherent magnetic switching, and increased signal. It may provide a read head element with more spatially coherent magnetic properties for high speed and processional or coherent magnetic sensing, and increased signal.
Type:
Grant
Filed:
November 6, 2003
Date of Patent:
June 27, 2006
Assignee:
Interuniversitair Microelektronica Centrum (IMEC)
Inventors:
Wayne Hiebert, Jo De Boeck, Liesbet Lagae, Roel Wirix-Speetjens
Abstract: An optical waveguide to fiber coupler comprises a substrate, a first waveguide and a second waveguide. The first and second waveguides are formed on the substrate and intersect at a right angle. A diffraction grating structure is formed at the intersection of the first and second waveguides, such that, when the coupler is physically abutted with a single mode optical fiber, in operation, a polarization split is obtained that couples orthogonal modes from the single-mode optical fiber into single identical modes in the first and second waveguides. Also, employing the coupler in optical polarization diverse applications provides for implementing a polarization insensitive photonic integrated circuit using such diffraction grating structures, such as, for example, photonic crystals.
Type:
Grant
Filed:
April 10, 2003
Date of Patent:
June 20, 2006
Assignee:
Interuniversitair Microelektronica Centrum (IMEC vzw)
Abstract: A method for forming macropores in a substrate is disclosed. On a substrate a pattern of submicron features is formed. This pattern is covered with a layer, which is preferably selectively removable with respect to the substrate and the submicron features. This cover layer is removed until the submicron features are exposed. The submicron features are then etched selectively to the cover layer, thereby creating a pattern of submicron openings in this cover layer. The patterned cover layer is used as a hardmask to etch macropores in the substrate.
Type:
Grant
Filed:
January 28, 2005
Date of Patent:
June 13, 2006
Assignee:
Interuniversitair Microelektronica Centrum (IMEC)
Abstract: Alternative laser structures, which have potentially the same tuning performance as (S)SG-DBR and GCSR lasers, and a fabrication process which is similar to that of the (S)SG-DBR laser, are presented. The advantage of these structures is that the output power does not pass through a long passive region.
Type:
Grant
Filed:
November 25, 2003
Date of Patent:
June 6, 2006
Assignee:
Interuniversitair Microelektronica Centrum (IMEC vzw)
Abstract: The present invention discloses a quantum system comprising computational elements, consisting of an insulated ring of superconductive material, and semi-closed rings, which are used as an interface or input/output facility between the quantum bit and the external world. Faraday induction is used to provide electromagnetic coupling between adjacent computational elements and between the computational elements with interface elements of the quantum system. Therefore the corresponding magnetic flux acts as an information carrier. Ferromagnetic cores are used to improve the magnetic coupling between adjacent elements of the quantum system.
Type:
Grant
Filed:
June 20, 2003
Date of Patent:
May 9, 2006
Assignees:
Interuniversitair Microelektronica Centrum (IMEC), Katholieke Universiteit Leuven
Inventors:
Wim Magnus, Christoph Kerner, Wim Schoenmaker
Abstract: Method for the production of airgaps in a semiconductor device, the semiconductor device comprising a stack of layers, the stack of layers comprising at least one iteration of a sub-stack of layers.
Type:
Grant
Filed:
September 30, 2004
Date of Patent:
May 2, 2006
Assignee:
Interuniversitair Microelektronica Centrum (IMEC vzw)
Inventors:
Jean Paul Gueneau de Mussy, Gerald Beyer, Karen Maex
Abstract: The present invention is related to a method for producing semiconductor devices from a semiconductor substrate, comprising providing a substrate having on its surface a number of elevated areas separated by areas which are at a lower level. Each elevated area has at its top surface a first layer of a material which is resistant to Chemical Mechanical Polishing (CMP). The method further comprises depositing a layer of a dielectric on top of the whole of said substrate, thereby filling the gaps between said elevated areas. The method further comprises depositing a second layer of a material which is resistant to CMP on top of the whole of said substrate. The method further comprises removing parts of the second CMP resistant layer and of dielectric layer. The method further comprises performing a CMP step and terminating the CMP step at the location of said first and second CMP resistant layers.
Type:
Grant
Filed:
June 27, 2002
Date of Patent:
April 25, 2006
Assignee:
Interuniversitair Microelektronica Centrum (IMEC)
Abstract: The present invention is related to an Electrostatic Discharge protection device. This may be a semiconductor device such as a CMOS transistor, having a snap-back IV characteristic, in order to withstand ESD pulses. The device of the invention comprises an additional doped region, which influences the internal resistance of the substrate whereupon the device is built. This has a positive effect on the snap-back characteristic, putting the snap back trigger voltage and current at a lower value, compared to prior art devices.
Type:
Grant
Filed:
August 29, 2003
Date of Patent:
April 18, 2006
Assignee:
Interuniversitair Microelektronica Centrum (IMEC)
Inventors:
Vesselin K. Vassilev, Guido Groeseneken