Patents Assigned to InterUniversitaire Microelektronica
  • Patent number: 6908856
    Abstract: The invention relates to a method for the fabrication of a device comprising electrical through hole interconnects. In one embodiment, the method comprises anisotropical dry etching of a patternable dielectric material within a substrate hole. One aspect of the invention provides a novel method for producing via or through hole interconnects between microelectronic elements, which is relatively easy to perform and can be applied relatively cheaply compared to the state of the art. The method should, for instance, be applicable in thin chip technology as MCM (Multi Chip Module) and system in a package (SIP) technology.
    Type: Grant
    Filed: April 2, 2004
    Date of Patent: June 21, 2005
    Assignee: Interuniversitair Microelektronica Centrum (IMEC)
    Inventors: Eric Beyne, Riet Labie
  • Patent number: 6906400
    Abstract: A semiconductor device is provided comprising a semiconductor substrate having on its top a Thin Strain Relaxed Buffer. The Thin Strain Relaxed Buffer consists of a stack of three layers of essentially constant Ge concentration. The three layers include a first epitaxial layer of Si1-xGex, a second epitaxial layer of Si1-xGex:C, and a third epitaxial layer of Si1-xGex on the second epitaxial layer. A method to fabricate such a buffer is also provided.
    Type: Grant
    Filed: January 13, 2004
    Date of Patent: June 14, 2005
    Assignees: Interuniversitair Microelektronica Centrum (IMEC), Koninklijke Philips Electronics
    Inventors: Romain Delhougne, Roger Loo, Philippe Meunier-Beillard, Mathieu Caymax
  • Patent number: 6900140
    Abstract: A method for forming an opening in an organic insulating layer by covering the insulating layer with a bilayer containing a resist hard mask layer and a resist layer on top of the resist hard mask layer. The bilayer is patterned, and an opening is created by plasma etching the insulating layer in a reaction chamber containing a gas mixture. The plasma etching is controlled so that virtually no etch residues are deposited and so that the side walls of the opening are fluorinated to enhance the anisotropy of the etching. The gas mixture can be a mixture of a fluorine-containing gas and an inert gas, a mixture of an oxygen-containing gas and an inert gas, or a mixture of hydrogen bromide and an additive.
    Type: Grant
    Filed: March 12, 2004
    Date of Patent: May 31, 2005
    Assignee: Interuniversitair Microelektronica Centrum (IMEC)
    Inventors: Serge Vanhaelemeersch, Mikhail Rodionovich Baklanov
  • Patent number: 6897517
    Abstract: A memory is described having a semiconductor substrate of a first conductivity type, a first and a second junction region of a second conductivity type, whereby said first and said second junction region are part of respectively a first and a second bitline. A select gate is provided which is part of a wordline running perpendicular to said first and said second bitline. Read, write and erase functions for each cell make use of only two polysilicon layers which simplifies manufacture and each memory cell has at least two locations for storing a charge representing at least one bit.
    Type: Grant
    Filed: June 24, 2003
    Date of Patent: May 24, 2005
    Assignees: Interuniversitair Microelektronica Centrum (IMEC), Infineon AG
    Inventors: Jan Van Houdt, Luc Haspeslagh
  • Publication number: 20050093154
    Abstract: In accordance with an embodiment of the invention, a FinFET device is disclosed which comprises a strained silicon channel layer formed on, at least, the sidewalls of a strain-relaxed silicon-germanium body.
    Type: Application
    Filed: July 26, 2004
    Publication date: May 5, 2005
    Applicant: Interuniversitair Microelektronica Centrum (IMEC vzw)
    Inventors: Anil Kottantharayil, Roger Loo
  • Patent number: 6885570
    Abstract: The present invention is related to the realization of a simplified bottom electrode stack for ferroelectric memory cells. More particularly, the invention is related to ferroelectric memory cells wherein the ferroelectric capacitor is positioned directly on top of a contact plug.
    Type: Grant
    Filed: November 8, 2002
    Date of Patent: April 26, 2005
    Assignees: Interuniversitair Microelektronica Centrum vzw (IMEC vzw), STMicroelectronics
    Inventors: Dirk Wouters, Jean-Luc Everaert, Judit Lisoni
  • Publication number: 20050079291
    Abstract: A method for depositing a coating layer on at least a part of a surface of a substrate is described. The method includes supplying a coating substance to at least part of a surface of a substrate. The substrate is subjected to a relative movement with respect to a source of the coating substance. The surface tension of the coating substance is modified, at least locally, at least part of the time while the at least part of the substrate is subjected to the movement. A thickness of the coating layer is influenced by modifying the surface tension of the coating substance.
    Type: Application
    Filed: June 30, 2004
    Publication date: April 14, 2005
    Applicant: Interuniversitair Microelektronica Centrum (IMEC), a Belgium Corporation
    Inventors: Wim Fyen, Paul Mertens
  • Publication number: 20050074960
    Abstract: Method for the production of airgaps in a semiconductor device, the semiconductor device comprising a stack of layers, the stack of layers comprising at least one iteration of a sub-stack of layers.
    Type: Application
    Filed: September 30, 2004
    Publication date: April 7, 2005
    Applicant: Interuniversitair Microelektronica Centrum (IMEC vzw)
    Inventors: Jean Gueneau de Mussy, Gerald Beyer, Karen Maex
  • Publication number: 20050074961
    Abstract: A method for the production of airgaps in a semiconductor device and device produced therefrom. The formation of airgaps is accomplished, in part, by chemically and/or mechanically changing the properties of a first dielectric layer locally, such that at least part of said first dielectric layer is converted locally and becomes etchable by a first etching substance. The local conversion of the dielectric material may be achieved during anisotropic etching of the material in oxygen containing plasma or ex-situ by performing an oxidizing step (e.g., a UV/ozone treatment or supercritical carbon dioxide with addition of an oxidizer). Formation of airgaps is achieved after creation of conductive lines and, alternatively, a barrier layer by a first etching substance. The airgaps are formed in a dual damascene structure, near the vias and/or the trenches of the damascene structure.
    Type: Application
    Filed: September 30, 2004
    Publication date: April 7, 2005
    Applicants: Interuniversitair Microelektronica Centrum (IMEC vzw), Texas Instruments, Inc.
    Inventors: Gerald Beyer, Jean Gueneau de Mussy, Karen Maex, Victor Sutcliffe
  • Patent number: 6876056
    Abstract: An interconnect module and a method of manufacturing the same is described comprising: a substrate, an interconnect section formed on the substrate, and a variable passive device section formed on the substrate located laterally adjacent to the interconnect section. The interconnect section has at least two metal interconnect layers separated by a dielectric layer and the variable passive device has at least one moveable element. The moveable element is formed from a metal layer which is formed from the same material and at the same time as one of the two interconnect layers. The moveable element is formed on the dielectric layer and is released by local removal of the dielectric layer. Additional interconnect layers and intermediate dielectric layers may be added.
    Type: Grant
    Filed: April 18, 2002
    Date of Patent: April 5, 2005
    Assignee: Interuniversitair Microelektronica Centrum (IMEC)
    Inventors: Hendrikus Tilmans, Eric Beyne, Henri Jansen, Walter De Raedt
  • Publication number: 20050068075
    Abstract: A charge pump circuit and method for supplying power. The charge pump circuit includes a first circuit receiving at least one low voltage signal and generating an output voltage signal. The charge pump circuit also includes a second circuit receiving a clock signal and the output voltage signal. The second circuit sends a request signal based on a comparison of the output voltage signal with two reference voltage signals, where the two reference voltage signals are derived from two supply voltage signals having a substantially constant potential difference. The charge pump circuit further includes a high voltage generator receiving the request signal and sending the two supply voltage signals to the first circuit and the second circuit. The high voltage generator adjusts the voltage potentials of the two supply voltage signals such that the voltage potential of the output voltage signal falls between the voltage potentials of the two reference voltage signals.
    Type: Application
    Filed: August 30, 2004
    Publication date: March 31, 2005
    Applicant: Interuniversitair Microelektronica Centrum (IMEC vzw)
    Inventor: Manuel Innocent
  • Patent number: 6872295
    Abstract: The present invention is related to a method for the preparation of a composition for electroplating a copper-containing layer on a substrate. This method makes use of an aqueous solution that has at least: a source of copper Cu(II) ions, an additive to adjust the pH to a predetermined value, and a complexing agent for complexing Cu(II) ions. The complexing agent has the chemical formula: COOR1—COHR2R3 in which R1 is an organic group covalently bound to the carboxylate group (COO), R2 is either hydrogen or an organic group, and R3 is either hydrogen or an organic group. The solution has no reducing agent. The method involves providing electrons from a source not in direct contact with the solution, through transport means that provides the contact between said source and said solution. The present invention is also related to a process for forming a copper-containing layer on a substrate in an electroplating bath prepared according to the foregoing method.
    Type: Grant
    Filed: December 12, 2001
    Date of Patent: March 29, 2005
    Assignee: Interuniversitair Microelektronica Centrum (IMEC)
    Inventors: Roger Palmans, Yuri Lantasov
  • Publication number: 20050051812
    Abstract: A multiple gate semiconductor device. The device includes at least two gates. The dopant distribution in the semiconductor body of the device varies from a low value near the surface of the body towards a higher value inside the body of the device.
    Type: Application
    Filed: July 16, 2004
    Publication date: March 10, 2005
    Applicant: Interuniversitair Microelektronica Centrum (IMEC vzw)
    Inventors: Abhisek Dixit, Kristin Meyer
  • Patent number: 6863795
    Abstract: The invention is related to a method of plating of a metal layer on a substrate. The method is particularly preferred for the formation of metallization structures for integrated circuits.
    Type: Grant
    Filed: March 21, 2002
    Date of Patent: March 8, 2005
    Assignee: Interuniversitair Microelektronica Centrum (IMEC)
    Inventors: Ivo Teerlinck, Paul Mertens
  • Patent number: 6859058
    Abstract: Test circuitry and test methods performing supply current measurement is presented. The test circuitry can be but is not limited to be on-chip. The supply current, also denoted test current, can be transient. The test circuitry and methods do not cause additional power supply voltage degradation. The test circuitry and methods provide detection capabilities for open defects, causing significant reduction of the transient supply current.
    Type: Grant
    Filed: September 30, 2002
    Date of Patent: February 22, 2005
    Assignee: Interuniversitair Microelektronica Centrum (IMEC UZW)
    Inventors: Hans Manhaeve, Stopjakova Viera
  • Patent number: 6855605
    Abstract: A method of forming layers, in the same device material, with different thickness or layer height in a semiconductor device comprises forming device material layer or gate electrode layer disposable parts in selected regions of the device layer. The disposable parts can be formed by doping the selected regions to the desired depth d. The as-deposited thickness t of this device layer can be adjusted or modulated after the patterning of the individual devices by removing the disposable parts.
    Type: Grant
    Filed: October 30, 2002
    Date of Patent: February 15, 2005
    Assignee: Interuniversitair Microelektronica Centrum (IMEC)
    Inventors: Malgorzata Jurczak, Rita Rooyackers, Emmanuel Augendre, Goncal Badenes
  • Patent number: 6851435
    Abstract: A method and apparatus for dispensing a liquid on the surface of a localized zone of a substrate, for example for cleaning of etching purposes. Along with the liquid, a gaseous tensio-active substance is supplied, which is miscible with said liquid and when mixed with the liquid, reduces the surface tension of said liquid, thus containing the liquid in a local zone of the substrate surface.
    Type: Grant
    Filed: February 13, 2002
    Date of Patent: February 8, 2005
    Assignee: Interuniversitair Microelektronica Centrum (IMEC, vzw)
    Inventors: Paul Mertens, Marc Meuris, Marc Heyns
  • Publication number: 20050014350
    Abstract: The present invention relates to methods for producing a patterned thin film on a substrate. The method comprises the spatially and possibly also temporally modulation of nucleation modes of film growth during the growth of patterned thin films. The nucleation modes are modulated between no or substantially no nucleation, 2D nucleation, and 3D nucleation. The modulation is obtained by adjusting the surface treatment spatially applied over regions of the substrate, the growth conditions for the thin film materials used, and/or the specific thin film materials used. The growth conditions typically comprise the substrate temperature and the deposition flux. The modulation allows for spatially varying the interaction between the substrate material and the thin film materials deposited.
    Type: Application
    Filed: July 6, 2004
    Publication date: January 20, 2005
    Applicant: Interuniversitair Microelektronica Centrum (IMEC), a Belgium Corporation
    Inventors: Paul Heremans, Dimitri Janssen, Soren Steudel, Stijn Verlaak
  • Patent number: 6844266
    Abstract: A method for anisotropic plasma etching of organic-containing insulating layers is disclosed. According to this method at least one opening is created in an organic-containing insulating layer formed on a substrate. These openings are created substantially without depositing etch residues by plasma etching said insulating layer in a reaction chamber containing a gaseous mixture which is composed such that the plasma etching is highly anisotropic. Examples of such gaseous mixtures are a gaseous mixture comprising a fluorine-containing gas and an inert gas, or a gaseous mixture comprising an oxygen-containing gas and an inert gas, or a gaseous mixture comprising HBr and an additive. The plasma etching of the organic-containing insulating layer can be performed using a patterned bilayer as an etch mask, said bilayer comprising a hard mask layer, being formed on said organic-containing insulating layer, and a resist layer being formed on said hard mask layer.
    Type: Grant
    Filed: March 12, 2003
    Date of Patent: January 18, 2005
    Assignee: Interuniversitair Microelektronica Centrum
    Inventors: Karen Maex, Ricardo A. Donaton, Michael Baklanov, Serge Vanhaelemeersch, Herbert Struyf, Marc Schaekers
  • Publication number: 20050002141
    Abstract: An electrostatic discharge (ESD) protection circuit for the protection of an electronic circuit from an ESD event. The electronic circuit, in operation, is provided with a supply voltage and a reference voltage (typically electrical ground) via voltage terminals and/or power supply buses. The protection circuit includes two bipolar transistors in series, where the transistors are coupled between the supply voltage terminal/bus and the reference voltage terminal/bus. The bases of the transistors are coupled via a connection including two resistors in series, where the connection point between the two resistors is coupled with the connection point between the two transistors.
    Type: Application
    Filed: May 28, 2004
    Publication date: January 6, 2005
    Applicants: Interuniversitair Microelektronica Centrum (IMEC vzw), AMI Semiconductor
    Inventors: Koen Reynders, Mahmud Zubeidat, Vincent De Heyn