Patents Assigned to Kabushiki Kaisha Nihon Micronics
  • Publication number: 20160146885
    Abstract: A probe comprises a first end that contacts and separates from a test object and a second end that contacts a circuit board to perform inspection of the test object. The second end is provided with a rotation restricted portion that restricts rotation of the probe about the axial direction thereof. An extendable portion, which is freely extendable and contractible in the axial direction of the probe and has at least one spiral slit, is provided between the first end and the second end. The second end is formed by a tubular member. Also, at least two of the extendable portions are provided between the first end and the second end, and an intermediate portion is formed between the extendable portions.
    Type: Application
    Filed: November 19, 2015
    Publication date: May 26, 2016
    Applicant: KABUSHIKI KAISHA NIHON MICRONICS
    Inventors: Hiroyasu ANDO, Mika NASU
  • Patent number: 9341651
    Abstract: A probe card for an electric test of a device under test on a working table incorporating a heat source includes a circuit base plate including conductive paths connected to a tester, a probe base plate including conductive paths corresponding to the conductive paths and provided with probes connected to the conductive paths, and a heat expansion adjusting member bonded to the probe base plate, having a different linear expansion coefficient from that of the probe base plate to restrain heat expansion of the probe base plate, and constituting a composite body with the probe base plate. In a case where, when the device under test is at two measuring temperatures, the composite body is at corresponding achieving temperatures, expansion changing amounts of the device under test and the composite body under temperature differences between the respective measuring temperatures and the corresponding achieving temperatures are set to be approximately equal.
    Type: Grant
    Filed: May 22, 2014
    Date of Patent: May 17, 2016
    Assignee: Kabushiki Kaisha Nihon Micronics
    Inventors: Osamu Arai, Yuki Saito, Tatsuo Inoue, Hidehiro Kiyofuji
  • Patent number: 9329206
    Abstract: A method for manufacturing a probe card is provided wherein probes are held in a holding plate such that the respective probes correspond to through holes with their connecting end portions projected from one surface of the holding plate. A plate-like member including openings having larger diameters than diameters of the through holes and housing the connecting end portions in the openings is arranged by making one surface of the plate-like member abut the one surface of the holding plate. After supplying solder cream in the respective openings from the other surface of the plate-like member, a connection base plate and the holding plate are relatively fixed so that the solder cream, burying the connecting end portions of the respective probes held in the holding plate with the plate-like member removed, may abut the respective corresponding connection pads, and the solder cream is heated to melt the solder cream.
    Type: Grant
    Filed: November 8, 2012
    Date of Patent: May 3, 2016
    Assignee: Kabushiki Kaisha Nihon Micronics
    Inventors: Tomokazu Saito, Yuki Kasai
  • Patent number: 9271393
    Abstract: A multilayer wiring base plate includes an insulating plate including a plurality of synthetic resin layers made of an insulating material, a wiring circuit provided in the insulating plate, a thin-film resistor formed along at least one of the synthetic resin layers to be buried in the synthetic resin layer and inserted in the wiring circuit, and a heat expansion and contraction restricting layer formed to be buried in the synthetic resin layer adjacent to the synthetic resin layer in which the thin-film resistor is formed to be buried, arranged along the thin-film resistor, and having a smaller linear expansion coefficient than a linear expansion coefficient of the adjacent synthetic resin layers.
    Type: Grant
    Filed: July 16, 2013
    Date of Patent: February 23, 2016
    Assignee: Kabushiki Kaisha Nihon Micronics
    Inventors: Noboru Otabe, Toshinori Omori, Takayasu Sugai
  • Patent number: 9215810
    Abstract: In a method for manufacturing a circuit board, as a photomask adapted to form an etching mask for selective removal of a seed layer covering a conductive portion exposed on an insulating film, a photomask whose opening area has an outline having two sides along two straight lines approaching to each other as the two straight lines extend from a center portion of the opening area in an extending direction of a wiring path is used.
    Type: Grant
    Filed: February 6, 2013
    Date of Patent: December 15, 2015
    Assignee: Kabushiki Kaisha Nihon Micronics
    Inventor: Ken Hasegawa
  • Patent number: 9207260
    Abstract: The present invention provides a probe block, which comprises 1) a conductive base on which a first groove is formed, 2) a pair of signal transmitting probes which have dielectric covers and are placed parallel to each other in the first groove, and 3) a ground probe which is in contact with the conductive base, wherein front portions of the signal transmitting probes and the ground probe protrude from the conductive base to form signal transmitting probe needles and a ground probe needle, respectively. The probe block of the present invention has excellent high frequency responses characteristics and is easy for maintenance.
    Type: Grant
    Filed: November 7, 2012
    Date of Patent: December 8, 2015
    Assignee: KABUSHIKI KAISHA NIHON MICRONICS
    Inventors: Takashi Ogasawara, Norie Yamaguchi
  • Patent number: 9194886
    Abstract: A probe is provided with a linear main body portion having a tip in contact with an electrode of a member to be tested in a state where a board-side end is in contact with the circuit board side of a probe card. An elastic support portion is provided on a board-side end portion of the main body portion and elastically supports the main body portion on the probe card side. The support portion has its base end side integrally fixed to the board-side end portion and is formed with the distal end side directed toward the tip portion of the main body portion and curved having an arc shape toward the main body portion side. Two pieces of the support portion are provided symmetrically on both sides sandwiching the board-side end portion and are configured by being curved, each having an arc shape with the same radius of curvature.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: November 24, 2015
    Assignee: Kabushiki Kaisha Nihon Micronics
    Inventor: Minoru Sato
  • Patent number: 9164130
    Abstract: A method for manufacturing a probe, includes forming a recess on a sacrificial layer with a resist matching a plane pattern of the probe and a fixing tab connected to the probe, the recess exposing the sacrificial layer, which is on a baseboard, forming the probe and the fixing tab connected to the probe by depositing a probe material in the recess, and removing the resist, removing a portion of the sacrificial layer in an etching process. The portion of the sacrificial layer under the probe is fully removed, while the portion of the sacrificial layer under the fixing tab is left to provide support portions of the sacrificial layer under the fixing tab. Then the probe is removed from the baseboard.
    Type: Grant
    Filed: October 21, 2013
    Date of Patent: October 20, 2015
    Assignee: KABUSHIKI KAISHA NIHON MICRONICS
    Inventor: Mika Nasu
  • Patent number: 9164149
    Abstract: This invention provide a testing device and method for a quantum battery by a semiconductor probe, whereby the electrical characteristics of the charging layer can be evaluated during the quantum battery manufacturing process. The testing device equipped with a semiconductor probe constituted by a conductive electrode and a metal oxide semiconductor layer including a metal oxide semiconductor which are laminated on a support, a source voltage for applying voltage across an electrode equipped to the semiconductor probe and a basic electrode laminated on a secondary battery charging layer, and an ammeter for measuring the current flowing between the electrode equipped on the semiconductor probe and the basic electrode of the secondary battery on which charging layer is laminated, and measures the current-voltage characteristics of the charging layer.
    Type: Grant
    Filed: October 30, 2011
    Date of Patent: October 20, 2015
    Assignees: Kabushiki Kaisha Nihon Micronics, Guala Technology Co., Ltd.
    Inventors: Harutada Dewa, Kiyoyasu Hiwada, Akira Nakazawa, Nobuaki Terakado
  • Patent number: 9146257
    Abstract: A contact probe electrically connects the tester side and an electrode pad of a circuit to be tested. This contact probe has a mounting portion on a base end portion mounted on a probe card, a contact portion on a distal end portion brought into contact with the electrode pad, and an arm portion between them elastically supporting the contact portion. The contact portion is provided on a lower end portion of a base portion integrally mounted on a distal end portion of the arm portion. The arm portion has a one-side arm piece supporting the base portion and allowing vertical movement of the base portion and the other-side arm piece supporting the base portion and adjusting an inclination angle of the base portion to reduce a scrub amount of the contact portion. The probe card uses the above-described contact probe.
    Type: Grant
    Filed: August 7, 2013
    Date of Patent: September 29, 2015
    Assignee: Kabushiki Kaisha Nihon Micronics
    Inventors: Masatomo Uebayashi, Akira Souma
  • Patent number: 9146256
    Abstract: A probe assembly for inspecting power semiconductor devices, which includes a probe block having more than one probe holding hole, more than one probe, each of which is contained in one of the probe holding holes with its outer surface being in contact with the inner surface of the probe holding hole, and which has lower end protruding from the probe block and coming into contact with the power semiconductor device on inspection, and one or more cooling units which cool the probe block. According to the probe assembly and the inspection apparatus, it is possible to inspect characteristics of power semiconductor devices accurately by suppressing temperature rises of the probes as well as the power semiconductor device under test.
    Type: Grant
    Filed: December 5, 2012
    Date of Patent: September 29, 2015
    Assignee: KABUSHIKI KAISHA NIHON MICRONICS
    Inventors: Katsuo Yasuta, Hikaru Masuta, Hideki Nei, Tatsuya Ishiwatari
  • Patent number: 9121869
    Abstract: Quality of connection portions between respective probes and respective wires in a probe assembly is improved. Also, time required for work for connection between the probes and the wires is shortened. Further, improper connection between the probes and the wires is eliminated. A probe assembly includes an electric insulating substrate, a plurality of probes supported on one surface of the substrate, a plurality of through holes provided in the substrate to respectively correspond to the plurality of probes and filled with a conductive material attached to the respective probes, and a plurality of conductive membranes formed on the other surface of the substrate and respectively attached to the conductive material in the plurality of through holes.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: September 1, 2015
    Assignee: Kabushiki Kaisha Nihon Micronics
    Inventors: Satoshi Narita, Kenji Sasaki
  • Patent number: 9116169
    Abstract: One plate-like member and the other plate-like member to be aligned with each other are provided with guide holes and guide portions to be received in the guide holes, respectively. The plate-like members are aligned appropriately, and in a state in which this alignment is held, the guide portions are formed on land portions provided on the other plate-like member so as to be aligned with the guide holes. Accordingly, regardless of presence/absence or size of a process error in the guide holes, the guide portions appropriate to the respective guide holes can be formed. Consequently, by aligning the guide portions with the guide holes, the plate-like members can be aligned appropriately without relative fine adjustment between the members.
    Type: Grant
    Filed: August 28, 2014
    Date of Patent: August 25, 2015
    Assignee: Kabushiki Kaisha Nihon Micronics
    Inventors: Tomokazu Saito, Seito Moriyama
  • Patent number: 9116174
    Abstract: An electrical connecting apparatus includes a wiring base plate having a first surface coupled with a reinforcing plate and provided on an opposite surface with first electrical connection portions, a probe base plate provided on a first surface with second electrical connection portions corresponding to the first electrical connection portions and provided on a second surface with probes electrically connected to the second electrical connection portions, anchor portions formed on the first surface of the probe base plate and provided with screw holes, cylindrical spacers having first ends removably coupled with the anchor portions, having screw grooves, and passing through the wiring base plate and the reinforcing plate, reference plates having reference planes to receive the spacers and removably coupled with the reinforcing plate, shims inserted between the respective reference plates and the reinforcing plate, and bolt screwed in the screw groove of the spacer.
    Type: Grant
    Filed: January 11, 2013
    Date of Patent: August 25, 2015
    Assignee: Kabushiki Kaisha Nihon Micronics
    Inventor: Kentaro Tanaka
  • Patent number: 9110098
    Abstract: Provided is a probe card capable of effectively placing electronic parts. A probe card according to the present invention includes a plurality of probes that come into contact with a plurality of electrodes of a device, a probe board including the plurality of probes provided thereon, a wiring board that is placed facing a surface of the probe board opposite to a surface including the probes provided thereon, a connector that includes a connection pin and a holder, in which the connection pin electrically connects a line of the probe board and a line of the wiring board, and the holder holds the connection pin between the probe board and the wiring board, and a first electronic part that is mounted on a probe board side surface of the wiring board and placed in a mounting space formed by a through hole or a recess provided in the holder.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: August 18, 2015
    Assignee: Kabushiki Kaisha Nihon Micronics
    Inventors: Katsushi Mikuni, Yoshinori Kikuchi, Yoshihito Onuma, Toshiyuki Kudo
  • Patent number: 9113546
    Abstract: A method for manufacturing an electric film body is made by forming a film body to have a shape in accordance with a desired electric characteristic and includes a film forming process for forming an electric film body on a board layer, an electric characteristic measuring process for measuring an electric characteristic in a surface of the electric film body formed in the film forming process, an electric film body shape setting process for setting a shape of the electric film body based on the electric characteristic measured in the electric characteristic measuring process, and an electric film body forming process for forming the electric film body formed in the shape set in the electric film body shape setting process.
    Type: Grant
    Filed: August 28, 2013
    Date of Patent: August 18, 2015
    Assignee: KABUSHIKI KAISHA NIHON MICRONICS
    Inventors: Takayasu Sugai, Noboru Otabe
  • Patent number: 9097761
    Abstract: A plurality of chip stack devices having different external sizes can be tested accurately and efficiently with low cost. The present invention provides a chip stack device testing method testing a chip stack device configured by stacking a plurality of chips separated by dicing a substrate under test tested in a testing unit. A tray for chip stack devices having equal shape and external dimension to those of the undiced substrate under test is used, one or a plurality of the chip stack devices are attached and supported to an adhesive layer of the tray for chip stack devices to align the chip stack devices with positions of the respective chips of the undiced substrate under test, the tray for chip stack devices is installed in the testing unit in a similar manner to that in a test of the substrate under test, and the respective chip stack devices are tested.
    Type: Grant
    Filed: November 10, 2011
    Date of Patent: August 4, 2015
    Assignee: KABUSHIKI KAISHA NIHON MICRONICS
    Inventors: Katsuo Yasuta, Yuji Miyagi
  • Patent number: 9095071
    Abstract: Provided is a method for manufacturing a multi-layer wiring board and the multi-layer wiring board that are capable of suppressing variation in resistance values. The method according to the present invention is the method for manufacturing a multi-layer wiring board. The method includes forming a resistor thin film, measuring resistance distribution of the resistor thin film, calculating resistor width adjustment rates of the plurality of resistors according to the resistance distribution, forming a pattern of a protective film on the resistor thin film, in which the pattern of the protective pattern has pattern width according to the resistor width adjustment rate, forming a pattern of a plating film on the resistor thin film at a position exposed from the protective film, and etching the resistor thin film at a position exposed from the plating film and the protective film so as to pattern the resistor thin film.
    Type: Grant
    Filed: November 13, 2013
    Date of Patent: July 28, 2015
    Assignee: KABUSHIKI KAISHA NIHON MICRONICS
    Inventors: Yoshiyuki Fukami, Toshinori Omori, Katsushi Mikuni, Noriko Kon
  • Publication number: 20150192611
    Abstract: A testing device and method of a quantum battery by a semiconductor probe capable of evaluating electric characteristics of a charge layer in the middle of a production process of the quantum battery without damaging the charge layer. On semiconductor probe constituted by stacking electrode and metal oxide semiconductor on support body, and probe charge layer is formed of the same material as that of quantum battery and irradiated with ultraviolet rays. Forming probe charge layer of same material as that of quantum battery on semiconductor probe enables evaluation without damaging charge layer of the quantum battery. Testing device and method are provided which measure the charge/discharge characteristics of a charge layer in the middle of producing the quantum battery by a voltmeter and a constant current source or a discharge resistor by using the semiconductor probe including the probe charge layer.
    Type: Application
    Filed: May 31, 2012
    Publication date: July 9, 2015
    Applicants: GUALA TECHNOLOGY CO., LTD., KABUSHIKI KAISHA NIHON MICRONICS
    Inventors: Harutada Dewa, Kiyoyasu Hiwada, Akira Nakazawa
  • Patent number: 9075083
    Abstract: An electrode and wiring can be provided on an FPC board without restriction by a through hole. A probe card in which an FPC board of a probe assembly is fixed to the main board side by a clamp mechanism is provided. The clamp mechanism is provided with a fixing ring fixed to the main board side and on which the FPC board is mounted and a rotating ring screwed into the fixing ring and pressing a peripheral edge portion of the FPC board. In the fixing ring, a pressing ring pressed by screwing of the rotating ring for pressing the peripheral edge portion of the FPC board to the main board side is provided.
    Type: Grant
    Filed: May 17, 2013
    Date of Patent: July 7, 2015
    Assignee: KABUSHIKI KAISHA NIHON MICRONICS
    Inventors: Yoshihito Onuma, Yoshihito Kitabatake, Ken Hasegawa, Takayuki Kogawa