Abstract: The present invention provides a method for continuity test of integrated circuit. By using both pins of integrated circuit to measure a current of an electrostatic discharge device, the contact resistance of the integrated circuit can be obtained by calculating. The method comprises the steps: First, a DUT (device under test) is provided, and the DUT includes a second pin and the second pin connecting zero reference potential. Then, a voltage is applied to a first pin of DUT. Finally, the current through said first pin and said second pin would be measured. Therefore, the testing result of the DUT could be more precise and the quality of the DUT would be made sure.

Abstract: A testing system module for testing printed circuit board (PCB) includes at least one robot having a pogo pin for moving to a testing point of the PCB; a pressure detecting unit for detecting a current pressure value on the printed circuit board; and a control system for keeping the pogo pin to contact with the PCB with constant pressure.

Abstract: A coplanarity inspection device for a printed circuit board includes a base, a supporting disk, a driver, a printed circuit board, a light source, an image acquisition means, and a controller. The supporting disk is arranged on the base, and the driver rotates the supporting disk. The printed circuit board is placed on the supporting disk, and includes a to-be measured side facing downward. The light source projects light beams on the to-be measured side of the printed circuit board. The image acquisition means aims at a specific area of the to-be measured side for image acquisition. The controller is to control the driver, and to store image taken by the image acquisition means. As such, the coplanarity inspection device for a printed circuit board can be employed to inspect whether the coplanarity of the printed circuit board satisfies the standard of setting values in a certain range.

Abstract: A method for wafer analysis with artificial neural network and the system thereof are disclosed. The method of the system of the present invention has several steps, including: first of all, providing a test unit for wafer test and generating a plurality of test data; next, transmitting the test data to a processing unit for transferring to output data; then, comparing the output data with predictive value and modifying bias and making the output data close to the predictive value, and repeating the steps mentioned above to train this system; finally, analyzing wafers by the trained system. Using this system to analyze wafers not only saves time, but also reduces manpower and the risk resulting from artificial analysis.

Abstract: A semiconductor test equipment with concentric pogo towers is disclosed, which comprises a base, a tester head, an outer pogo tower, and an inner pogo tower. The inner pogo tower is concentrically received in the outer pogo tower, and a connecting slot of the inner pogo tower is correspondingly engaged with a connecting pin of the outer pogo tower. The outer pogo tower is fixed to the load board together with the inner pogo tower, whereby a plurality of outer pogo pins of the outer pogo tower and a plurality of inner pogo pins of the inner pogo tower are electrically connected to the load board respectively. Therefore, the present invention is capable of expanding the test specifications, but also to change rapidly from different test specifications through replacing a different probe card but without to modify any other hardware.

Abstract: In the present invention, a feeding apparatus comprising a plurality of feeding mechanisms is provided. The feeding apparatus comprises a power source, a base, a rotating axle, a plurality of feeding mechanisms, a plurality of connecting units and a plurality of fixing units. The power source is driven to rotate the rotating axle, and then the feeding mechanisms are rotated by the rotating axle to proceed feeding process. In addition, the rotation of each of the feeding mechanisms is controlled by the connecting units and the fixing units. However, the feeding mechanisms can be rotated together or individually to proceed feeding process. Therefore, the production capacity is increased by the feeding apparatus, as well as the cost is reduced by decreasing power needed.

Abstract: The present invention relates to a self-cleaning package testing socket, which comprises a base plate, a surround wall is configured on the periphery of the base plate and surrounding with a central testing tank inside. Two transversal channels respectively disposed at two opposite sides of the surround wall. Each transversal channel comprises a nozzle tube between inlet and outlet; the nozzle tube radially connects two bypass pipes. Herewith, the testing tank through the bypass pipes connected to the nozzle tubes of the transversal channels. Hence, when passing air into one end of the each transversal channel, it will cause the airflow rate inside the nozzle tube to speed up, so that the pressure inside the bypass pipes will reduce, and the testing tank results a vacuum-clean effect. Therefore, the present invention can be on-line self-cleaning the test socket.

Abstract: A semiconductor test system with self-inspection of memory repair analysis is disclosed, comprising a memory repair analysis device, an analysis fail memory and a self-inspection controller. The self-inspection controller controls storing a set of simulated fail bit addresses and a set of simulated repair line addresses, provided from outside, into the analysis fail memory in advance, controls the memory repair analysis device to execute a particular repair analysis operation with respect to the set of simulated fail bit addresses to produce repair line address information, and compares the repair line address information, obtained after calculation, directly with the set of simulated repair line addresses in the analysis fail memory. Thus, before physically proceeding with the operation of testing, the invention is capable of self-inspecting if there is an abnormal condition of the memory repair analysis device and the analysis fail memory contained therein.

Abstract: A semiconductor test equipment with concentric pogo towers is disclosed, which comprises a base, a tester head, an outer pogo tower, and an inner pogo tower. The inner pogo tower is concentrically received in the outer pogo tower, and a connecting slot of the inner pogo tower is correspondingly engaged with a connecting pin of the outer pogo tower. The outer pogo tower is fixed to the load board together with the inner pogo tower, whereby a plurality of outer pogo pins of the outer pogo tower and a plurality of inner pogo pins of the inner pogo tower are electrically connected to the load board respectively. Therefore, the present invention is capable of expanding the test specifications, but also to change rapidly from different test specifications through replacing a different probe card but without to modify any other hardware.

Abstract: The present invention relates to a self-cleaning package testing socket, which comprises a base plate, a surround wall is configured on the periphery of the base plate and surrounding with a central testing tank inside. Two transversal channels respectively disposed at two opposite sides of the surround wall. Each transversal channel comprises a nozzle tube between inlet and outlet; the nozzle tube radially connects two bypass pipes. Herewith, the testing tank through the bypass pipes connected to the nozzle tubes of the transversal channels. Hence, when passing air into one end of the each transversal channel, it will cause the airflow rate inside the nozzle tube to speed up, so that the pressure inside the bypass pipes will reduce, and the testing tank results a vacuum-clean effect. Therefore, the present invention can be on-line self-cleaning the test socket.

Abstract: A method for designing stacked pattern of PCB utilizing genetic algorithm and the system thereof are disclosed. The method comprises the following steps: First of all, information data of stacked pattern is inputted into operational interface of the software; Next, initial solution sets of stacked pattern are generated; Then, duplications of the initial solution sets of stacked pattern are generated according to a fitness function; Afterward, crossover of the duplications of stacked pattern are performed at random; Then, mutations are executed by a probability at random; Finally, identification is performed to check if the solution approaches the standard of demand and the result of stacked pattern is shown; otherwise, operational step jumps to duplicate step and repeats above steps until satisfying solution is obtained. The most suitable way for package can be arranged out through making especially mathematical calculations by the system efficiently.

Abstract: A semiconductor test system with self-inspection of an electrical channel for a Pogo tower is disclosed, which provides a short board and closed loops are formed respectively by providing various kinds of contacts to correspondingly electrically contact various kinds of Pogo pins in the Pogo tower on a load board. A self-inspection controller outputs different inspection signals, through the above-mentioned closed loops, respectively to each power channel, each I/O channel and each drive channel, and a plurality of parameter detection units detect response signals, and the response signals are judged by the self-inspection controller. Based on it, before inspecting a wafer to be tested, the invention is capable of self-inspecting each electrical channel and each Pogo pin on the Pogo tower to see if they are respectively in a normal condition, either in an open or short circuit, or if there exists a leakage condition.

Abstract: The present invention provides a parallel test fixture for mixed signal integrated circuits (ICs). The fixture includes a multi-layer printed circuit board (PCB). The fixture includes: a test area, which is disposed on a central area of the multi-layer PCB and includes several test regions for a plurality of mixed signal ICs; an analog signal ground layer, which is operationally connected with the analog signals of the mixed signal ICs in the test area; and a digital signal ground layer, which is operationally connected with the digital signals of the mixed signal ICs in the test area. Thereby, when a plurality of mixed signal ICs are parallel tested, not only the problem due to cross-talk could be solved but also the numbers of the layers of the multi-layer PCB could be reduced effectively.

Abstract: A probe card is disclosed, which has a conductive layer additionally provided on an insulating seat of a probe stand and the conductive layer is electrically connected to a ground circuit on the probe card via a conductive pin being fed through the insulating seat. A conductive wire is wound surrounding the intermediate segment of the probe, one end of the conductive wire is electrically connected to the ground circuit of the circuit board, and the other end of the conductive wire is electrically connected to the conductive layer of the probe stand. Thus, due to that an additional ground portion of the conductive layer is provided on the conductive wire wound surrounding the probe, a loop inductance of the probe in the insulating seat can be reduced such that accuracy of test data of the probe can be enhanced.

Abstract: A method and apparatus for improving yield ratio of testing are disclosed. The method includes the following steps. First of all, devices are tested and electromagnetic interference is measured. Next, the test results are examined for whether the devices pass the test or not. Then, electromagnetic interference data are examined for whether the electromagnetic interference data are over a predetermined standard if the devices fail the test. The above-mentioned steps are performed again if the electromagnetic interference data are over a predetermined standard. The test is terminated if the devices still fail the test and the values of electromagnetic interference are still over a predetermined standard.

Abstract: Discloses are a probe card assembly and test probes used therein. The probe card assembly includes a main body, a probe base disposed in a central portion of the main body and a plurality of test probes connected between the probe base and the main body. Each of the test probes has a tip extending from the probe base for contacting a wafer under test. The test probes include at least one power probe, at least one signal probe and a plurality of ground probes. Each of the test probes has a middle section interposed between the main body and the probe base. Each of the test probes except the ground probes has a naked middle section coated with an insulating film but not sheltered by an insulating sleeve.

Abstract: A semiconductor test system with self-inspection of memory repair analysis is disclosed, comprising a memory repair analysis device, an analysis fail memory and a self-inspection controller. The self-inspection controller controls storing a set of simulated fail bit addresses and a set of simulated repair line addresses, provided from outside, into the analysis fail memory in advance, controls the memory repair analysis device to execute a particular repair analysis operation with respect to the set of simulated fail bit addresses to produce repair line address information, and compares the repair line address information, obtained after calculation, directly with the set of simulated repair line addresses in the analysis fail memory. Thus, before physically proceeding with the operation of testing, the invention is capable of self-inspecting if there is an abnormal condition of the memory repair analysis device and the analysis fail memory contained therein.

Abstract: A semiconductor test system with self-inspection of an electrical channel for a Pogo tower is disclosed, which provides a short board and closed loops are formed respectively by providing various kinds of contacts to correspondingly electrically contact various kinds of Pogo pins in the Pogo tower on a load board. A self-inspection controller outputs different inspection signals, through the above-mentioned closed loops, respectively to each power channel, each I/O channel and each drive channel, and a plurality of parameter detection units detect response signals, and the response signals are judged by the self-inspection controller. Based on it, before inspecting a wafer to be tested, the invention is capable of self-inspecting each electrical channel and each Pogo pin on the Pogo tower to see if they are respectively in a normal condition, either in an open or short circuit, or if there exists a leakage condition.

Abstract: A semiconductor test system with self-inspection of an electrical channel is disclosed, which comprises a tester head, a plurality of parameter detection units and a self-inspection controller. The tester head includes a plurality of pin electronics cards inserted therein, in which the plurality of pin electronics cards contain a plurality of power channels, a plurality of I/O channels and a plurality of drive channels. The self-inspection controller outputs different inspection signals respectively to each power channel, each I/O channel and each drive channel. Then, the plurality of parameter detection units detect response signals respectively produced by each power channel, each I/O channel and each drive channel in response to the inspection signals respectively received thereby, and the response signals are judged by the self-inspection controller.

Abstract: The present invention discloses a probe card for testing a wafer. The probe card comprises a printed circuit board for transmitting test signals, a fastened ring arranged at the downside of the printed circuit board, and a plurality of needles passing through the fastened ring, each needle having one end connecting to circuits of the printed circuit board, and having a tip portion at the other end connecting to a pad of the wafer, where each needle has at least one bent portion between the fastened ring and the tip portion, to absorb stress between the needle and the pad.