Patents Assigned to Lattice Semiconductor Corporation
  • Patent number: 11138150
    Abstract: A method and apparatus for a network repository for metadata. Embodiments of a data repository include a memory to store data including one or more data content items, where each data content item is associated with zero or more metadata items, and where each data content item is associated with a handle and each metadata item is associated with an attribute name. The data repository further includes a network interface configured to communicate with a client device, and a control unit configured to control the storage of data in the memory, where the control unit provides functions for writing data to and reading data from the memory and where the control unit is to transfer the data without interpretation.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: October 5, 2021
    Assignee: Lattice Semiconductor Corporation
    Inventors: Brian K. Schmidt, James G. Hanko, J. Duane Northcutt
  • Patent number: 11132207
    Abstract: Various techniques are provided to implement fast boot for programmable logic devices (PLDs). In one example, a method includes receiving configuration data associated with a PLD. The PLD includes an array of configuration memory cells including logic block memory cells and input/output (I/O) block memory cells associated with the PLD's logic fabric and I/O fabric, respectively. The method further includes programming a subset of the I/O block memory cells with the configuration data, and providing a wakeup signal to activate functionality associated with a portion of the I/O fabric. The method further includes programming remaining configuration memory cells of the array with the configuration data, where the remaining configuration memory cells include at least a subset of the logic block memory cells. The method further includes providing a wakeup signal to activate functionality associated with at least a portion of the logic fabric. Related systems and devices are provided.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: September 28, 2021
    Assignee: LATTICE SEMICONDUCTOR CORPORATION
    Inventors: Fulong Zhang, Gordon Hands, Satwant Singh, Wei Han, Ravindar Lail, Joel Copien, Sreepada Hegade, Ming Hui Ding
  • Patent number: 10979083
    Abstract: Example embodiments herein relate to methods of transmitting and receiving audio signals. A method of transmitting an audio signal includes: receiving the audio signal including frames having left and right subframes containing audio data of a first number of bits; encoding the left and right subframes into a parity code of a second number of bits; generating serial data by combining the parity code and audio data; and transmitting the serial data over an audio transmission media having a bandwidth of a third number of bits, a sum of the first and second number being below the third number. A method of receiving an audio signal includes: receiving a serial signal combining a parity code; decoding the serial signal by calculating a syndrome based on the parity code; detecting an error by comparing the syndrome with the audio data; and generating a corrected audio signal by correcting the detected error.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: April 13, 2021
    Assignee: LATTICE SEMICONDUCTOR CORPORATION
    Inventors: Jiong Huang, Alexander Peysakhovich, Lei Ming
  • Patent number: 10931722
    Abstract: A source device and a sink device may be connected using an interface cable comprising at least first and second physical channels. The first physical channel may be used to transmit video data unidirectionally from the source device to the sink device. In addition, the second physical channel may comprise an audio return channel wherein audio data can be transmitted unidirectionally from the sink device to the source device at a first rate. In addition, the second physical channel may also transmit bidirectional control data between the source and sink devices at a second rate slower than the first rate. The audio data may be overlaid on the control data, wherein the audio data is transmitted using differential signaling, while the control data is transmitted using common mode signaling.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: February 23, 2021
    Assignee: LATTICE SEMICONDUCTOR CORPORATION
    Inventors: Shrikant Ranade, Lei Ming, Jiong Huang
  • Patent number: 10884452
    Abstract: Methods and circuitry for low-speed bus time stamping and triggering are presented in this disclosure. A master device and slave devices can be interfaced via a communication link that comprises a data line and a clock line. The master device generates and controls a clock signal on the clock line, and sends a synchronization command over the data line to the slave devices. In response to the synchronization command, the master device receives timestamp information of an event detected at each slave device. The master device tracks transitions and frequencies of the clock signal, and determines a time of the event based on the timestamp information, the tracked transitions and the frequencies. The master device can further send to each slave device delay setting information for generating a trigger signal at that slave device based on transitions of the clock signal, the synchronization command and the delay setting information.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: January 5, 2021
    Assignee: Lattice Semiconductor Corporation
    Inventor: Bradley Sharpe-Geisler
  • Patent number: 10868495
    Abstract: Some aspects of the present disclosure relate to an apparatus, a PLL and an electronic device. The apparatus comprises a voltage-to-current (V2I) converter, a current controlled oscillator and a compensation current. The V2I converter is operable to receive a first voltage and generate a first current based on the first voltage. The current controlled oscillator is coupled to the V2I converter and operable to generate an oscillation signal based on a second current from or to the V2I converter. The compensation circuit is coupled to the V2I converter and operable to receive a third current from or to the V2I converter. The second and third currents vary in response to at least one of temperature variation and supply voltage variation of the apparatus. Variation direction of the third current is opposite to variation direction of the second current and different frequencies may be provided for a low supply voltage domain.
    Type: Grant
    Filed: June 12, 2019
    Date of Patent: December 15, 2020
    Assignee: LATTICE SEMICONDUCTOR CORPORATION
    Inventors: Kai Lei, Shirley Li, Oliver Wu
  • Patent number: 10764026
    Abstract: Methods and circuitry for relatively low-speed bus time stamping and triggering for use in acoustic object and gesture detection and recognition are presented in this disclosure. A master device and slave devices can be interfaced via a communication link that includes a data line and a clock line. The master device generates and controls a clock signal on the clock line and sends a synchronization command over the data line to the slave devices. The master device receives timestamp and/or other information corresponding to events detected at each slave device, such as a detected acoustic wave reflected from an object. The master device tracks transitions and frequencies of the clock signal, and determines a time of the event based on the timestamp information, the tracked transitions and the frequencies. The master device can use the event times to derive positions and gestures associated with detected objects.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: September 1, 2020
    Assignee: LATTICE SEMICONDUCTOR CORPORATION
    Inventor: Bradley Sharpe-Geisler
  • Patent number: 10754401
    Abstract: In one embodiment, a reconfigurable and scalable hardware management architecture includes a digital controller for controlling two or more analog sense-and-control (ASC) circuits, where each ASC monitors voltage, current, and temperature of one or more power supplies, ICs, or a circuit board. The controller and ASCs are connected in a star architecture, where each ASC is connected to the controller via a different, dedicated interface to communicate regarding the power supplies being monitored. The controller and the ASCs are also connected in a bus architecture via a shared interface. The architecture can be re-configured by adding one or more additional ASCs or by removing one or more existing ASCs, where each additional ASC is (i) connected to a different I/O interface of the digital controller via a different, dedicated interface and (ii) connected to the digital controller and the two or more existing ASCs via the shared interface.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: August 25, 2020
    Assignee: LATTICE SEMICONDUCTOR CORPORATION
    Inventors: Srirama Chandra, Robert Bartel
  • Patent number: 10693463
    Abstract: Example embodiments of the present disclosure relate to a line driver apparatus. In some example embodiments, an apparatus is provided. The apparatus includes a capacitive feed-through module and a driving module. The capacitive feed-through module includes a first pre-driver operable to receive input differential signals and delayed signals of the input differential signals, generate first drive signals from the input differential signals and the delayed signals, and equalize the first drive signals. The capacitive feed-through module also includes a capacitance reducing module arranged between the first pre-driver and transmission lines and operable to reduce parasitic capacitance at the transmission lines in response to the first drive signals. The driving module is coupled to the transmission lines and operable to generate output differential signals from the input differential signals for transmission on the transmission lines.
    Type: Grant
    Filed: April 14, 2017
    Date of Patent: June 23, 2020
    Assignee: LATTICE SEMICONDUCTOR CORPORATION
    Inventor: Kexin Luo
  • Patent number: 10645199
    Abstract: A bridge chip receives a first data stream compliant with the first multimedia communication standard. The first data stream includes first video data of a first incoming video frame, second video data of a second incoming video frame, and information describing a transfer function for the second video data, the information included in a video blanking interval of the first incoming video frame. The bridge chip extracts information describing a transfer function for the second video data. The bridge chip then generates a second data stream compliant with the second multimedia communication standard. The second data stream includes the first video data in a first outbound video frame, the second video data in a second outbound video frame, and the extracted information describing the transfer function for the second video data. Finally, the generated second data stream is transmitted to a destination device.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: May 5, 2020
    Assignee: Lattice Semiconductor Corporation
    Inventors: Jiong Huang, Henry Tso, Hoon Choi
  • Patent number: 10637972
    Abstract: A sink device transmits capabilities information associated with the sink device to the source device. The source device, responsive to receiving the capabilities information of the sink device generates a multimedia stream, and transmits the generated multimedia stream to the sink device to be output to the user. The sink device identifies a portion of the capabilities information that has changed and transmits to the source device a notification notifying the source device that a portion of the capabilities information has changed. The source device transmits a request for the portion of the capabilities information that has changed to the sink device. The sink device responsive to receiving the request transmits the portion of the capabilities information that has changed to the source device. The source device then modifies the multimedia stream output to the sink device based on the portion of the capabilities information that has changed.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: April 28, 2020
    Assignee: Lattice Semiconductor Corporation
    Inventor: Sergey Yarygin
  • Patent number: 10630269
    Abstract: Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a programmable logic device (PLD) includes a plurality of programmable logic blocks (PLBs) and at least first and second logic cells within at least one of the PLBs, where each logic cell includes a lookup table (LUT) and associated mode logic configured to receive a LUT output signal from the LUT. The associated mode logic is configured to use a single physical signal output to provide a logic cell output signal corresponding to a selected logic function operational mode, ripple arithmetic operational mode, or extended logic function operational mode for each logic cell.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: April 21, 2020
    Assignee: Lattice Semiconductor Corporation
    Inventors: Brad Sharpe-Geisler, Senani Gunaratna, Ting Yew
  • Patent number: 10559357
    Abstract: One aspect relates to a memory circuit that has a programmable non-volatile memory (NVM) cell configured to generate an NVM output signal indicative of a program state of the NVM cell and to configure a volatile output based on the program state of the NVM cell. The NVM cell comprises a first magnetic tunnel junction (MTJ) device, a first select device connected in series with the first MTJ device at a first node, and a first pass device. The memory circuit also may have a programmable (independently of the NVM cell) volatile memory (VM) cell configured to receive the NVM output signal at a VM input node and to generate a VM output signal indicative of the program state of the VM cell.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: February 11, 2020
    Assignee: Lattice Semiconductor Corporation
    Inventor: Ronald L. Cline
  • Patent number: 10558236
    Abstract: A direct digital synthesizer (DDS) is controlled by a suitably configured programmable logic device (PLD). The DDS includes a digital analog converter (DAC), and a coupled driver/buffer configured to drive relatively high capacitive loads with substantially rail to rail sinusoidal driver output signals and with little to no waveform distortion. The DAC includes a PMOS and NMOS DACs, and a switch configured to select the PMOS DAC for negative portions and the NMOS DAC for positive portions of an output analog signal generated by the DAC. The driver includes a pair of input differential amplifiers, PMOS and NMOS structures, which may be variable, and a pair of variable current sources. The PLD controls variable elements of the DDS to adjust the achievable positive and negative slew rates of the DDS, independently of one another, to reduce or eliminate risk of signal distortion while maintaining substantially stable rail to rail output.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: February 11, 2020
    Assignee: Lattice Semiconductor Corporation
    Inventors: Vinh Ho, Magathi Jayaram Willis, Keith Truong, Hamid Ghezelayagh
  • Patent number: 10523153
    Abstract: A voltage controlled oscillator (VCO) is disclosed. The VCO includes an amplifier that receives a control signal and a feedback signal and generates an amplified output signal based on the difference between the control signal and the feedback signal. The VCO also includes circuitry to generate an oscillating output signal based on the amplifier output signal. Additionally, the VCO includes a feedback amplifier that generates the feedback signal based on the output of the amplifier. The feedback amplifier includes a first resistor connected in parallel with a second resistor, the second resistor having an adjustable resistance.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: December 31, 2019
    Assignee: Lattice Semiconductor Corporation
    Inventors: Qiming Wu, Yibin Fu, Yu Shen, Zhi Wu, Kai Lei, Kai Zhou, Kexin Luo, Xiaofeng Wang
  • Patent number: 10505735
    Abstract: Embodiments relate to inserting a preamble code as a preamble of a sub-frame of encrypted data to indicate rekeying is to be performed at a source device and to indicate data of the sub-frame and subsequent sub-frames is encrypted. A sink device authenticates a source device using an authentication and encryption protocol. The sink device receives a data stream including audio data. At least a portion of the received audio data is encrypted and the encrypted audio data is packetized into sub-frames. The sink device inserts a first preamble code as a preamble of a sub-frame to indicate rekeying is to be performed at the source device according to the authentication and encryption protocol, and to indicate that the audio data in a payload of the sub-frame and payloads of subsequent sub-frames is encrypted. The sink device transmits the packet to the source device via a first data link.
    Type: Grant
    Filed: December 7, 2015
    Date of Patent: December 10, 2019
    Assignee: Lattice Semiconductor Corporation
    Inventors: Ju Hwan Yi, Hoon Choi
  • Patent number: 10484036
    Abstract: Systems and methods for polarization converters are disclosed. An example wireless communication system includes a first transceiver module of a wireless communication system configured to form one or more linearly polarized communication links with a second transceiver module of the wireless communication system, and a polarization converter positioned between the first and second transceiver modules and configured to convert the one or more linearly polarized communication links to circularly polarized communication links. The polarization converter includes first and second frequency selective surfaces (FSSs) formed from respective first and second metalized layers of a printed circuit board (PCB), each FSS includes an array of capacitive patches and inductive traces forming an array of unit cells, and each unit cell of the second FSS is aligned with each unit cell of the first FSS.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: November 19, 2019
    Assignee: Lattice Semiconductor Corporation
    Inventors: Rongrong Lu, Ron Zeng
  • Patent number: RE48570
    Abstract: One aspect relates to a memory circuit that has a programmable non-volatile memory (NVM) cell configured to generate an NVM output signal indicative of a program state of the NVM cell and to configure a volatile output based on the program state of the NVM cell. The NVM cell comprises a first anti-fuse device, a first select device connected in series with the first anti-fuse device at a first node, and a first pass device. The memory circuit also may have a programmable (independently of the NVM cell) volatile memory (VM) cell configured to receive the NVM output signal at a VM input node and to generate a VM output signal indicative of the program state of the VM cell. The NVM cell may have two NV elements that are separately programmable and are separately selectable via separate access transistors to drive the VM input node.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: May 25, 2021
    Assignee: LATTICE SEMICONDUCTOR CORPORATION
    Inventors: Ronald L. Cline, Stewart G. Logie
  • Patent number: RE48625
    Abstract: One aspect relates to a memory circuit that has a programmable non-volatile memory (NVM) cell configured to generate an NVM output signal indicative of a program state of the NVM cell and to configure a volatile output based on the program state of the NVM cell. The NVM cell comprises a first anti-fuse device, a first select device connected in series with the first anti-fuse device at a first node, and a first pass device. The memory circuit also may have a programmable (independently of the NVM cell) volatile memory (VM) cell configured to receive the NVM output signal at a VM input node and to generate a VM output signal indicative of the program state of the VM cell. The NVM cell may have two NV elements that are separately programmable and are separately selectable via separate access transistors to drive the VM input node.
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: July 6, 2021
    Assignee: Lattice Semiconductor Corporation
    Inventors: Ronald L Cline, Stewart G. Logie
  • Patent number: RE48740
    Abstract: A solution for adaptively processing a digital image with reduced color resolution is described herein. A source device pre-processes a video frame with reduce color resolution by remapping luma components and chroma components of the video frame, and encodes the pre-processed video frame. The source device remaps a half of luma components on a scan line of the video frame onto a data channel of a source line to an encoder and remaps the other half of the luma components on the scan line to another data channel of the source line. The source device remaps the corresponding chroma components onto a third data channel of a source line. By using a data channel conventionally configured to transmit chroma components, the solution enables a video codec to adaptively encode a digital image with reduced color resolution without converting the digital image to full color resolution before the encoding.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: September 14, 2021
    Assignee: LATTICE SEMICONDUCTOR CORPORATION
    Inventor: Laurence Alan Thompson