Abstract: Various techniques are provided to efficiently implement deterministic read back and error detection for programmable logic devices (PLDs). In one example, a PLD includes an array of memory cells arranged in rows and columns, where at least one row includes an enable bit. The PLD further includes an address logic circuit configured to selectively assert the columns of the array by respective address lines. The PLD further includes a register configured to store a value of the enable bit in response to an assertion of an address line corresponding to the enable bit. The PLD further includes a read back circuit configured to selectively provide, for each memory cell, a data bit value stored by the memory cell or a predetermined data bit value based at least on the stored value of the register. Additional systems and related methods are provided.

Abstract: Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a programmable logic device (PLD) includes a plurality of programmable logic blocks (PLBs) and a plurality of logic cells within at least one of the PLBs, where each logic cell includes a four input lookup table (4-LUT) configured to provide a 4-LUT output signal to associated carry logic. Each logic cell is configurable according to at least two selectable operational modes including a logic function output mode and a ripple arithmetic output mode, and at least three of the 4-LUT inputs are interchangeable when a selected operational mode comprises the ripple arithmetic output mode.

Abstract: Various techniques are provided to implement hysteresis control for programmable logic devices (PLDs). In one example, a PLD includes a hysteresis control circuit configured to generate a hysteresis control signal based on a core voltage and an input/output (I/O) voltage. The PLD further includes an I/O cell associated with an I/O fabric of the PLD and powered by the I/O voltage. The I/O cell includes a first buffer circuit configured to receive an input voltage and generate a first buffer voltage based on the input voltage. The I/O cell further includes a hysteresis generator configured to generate a hysteresis voltage based on the hysteresis control signal and the I/O voltage. The I/O cell further includes a second buffer circuit configured to generate a second buffer voltage based on the first buffer voltage and the hysteresis voltage. Related methods and systems are provided.

Abstract: Various techniques are provided to efficiently implement user designs incorporating clock and/or data recovery circuitry and/or a deserializer in programmable logic devices (PLDs). In one example, a method includes receiving a serial data stream, measuring time periods between signal transitions in a serial data stream using at least one Grey code oscillator, and generating a recovered data signal corresponding to the serial data stream by, at least in part, comparing the measured time periods to one or more calibration time periods. In another example, a system includes a Grey code oscillator configured to increment a Grey code count between signal transitions in a serial data stream, and a Grey code converter configured to convert the Grey code count approximately at the signal transitions to a plurality of binary counts each corresponding to a time period between one or more signal transitions in the serial data stream.

Abstract: In one embodiment, a reconfigurable and scalable hardware management architecture includes a digital controller for controlling two or more analog sense-and-control (ASC) circuits, where each ASC monitors voltage, current, and temperature of one or more power supplies (e.g., DC-to-DC converters), ICs, or a circuit board. The controller and ASCs are connected in a star architecture, where each ASC is connected to the controller via a different, dedicated interface to communicate regarding the power supplies being monitored. In addition, the controller and the ASCs are also connected in a bus architecture via a shared interface. The architecture can be re-configured by adding one or more additional ASCs or by removing one or more existing ASCs, where each additional ASC is (i) connected to a different I/O interface of the digital controller via a different, dedicated interface and (ii) connected to the digital controller and the two or more existing ASCs via the shared interface.

Abstract: A source device includes a forward error correction encoder circuit to generate error correction protected blocks from video data packets. Each error correction protected block includes data words and error correction words. An encoder circuit encode X-bit words of the error correction protected blocks into Y-bit encoded words for transmission to a sink device over one or more multimedia lanes of a multimedia communication link, where X is smaller than Y.

Abstract: Systems and methods are disclosed herein to provide improved placement of components in programmable logic devices (PLDs). In one example, a computer-implemented method includes receiving a design identifying operations to be performed by a PLD. The method also includes determining a layout comprising positions of components of the PLD configured to perform the operations. The method also includes performing a timing analysis on the layout. The method also includes selectively adjusting the positions of the components using the timing analysis. Related systems and non-transitory machine-readable mediums are also provided.

Abstract: Embodiments relate to a voltage oscillator (VCO) that uses a replica bias circuit to generate a cascode bias voltage. The VCO generate an output periodic signal having a frequency and phase that is less or not susceptible to voltage swings by using a bias voltage generated in a replica bias circuit that replicates a voltage-to-current converter in the VOC. The bias voltage is generated and regulated according to a power supply voltage that supplies power to the VCO to account for voltage variations in the power supply voltage.

Abstract: A non-volatile programmable bitcell has a read enable device with a source coupled with a bitline, an anti-fuse device with a gate coupled with a first write line, a drain coupled with a supply voltage and a source coupled with a drain of the read enable device. The bitcell has a fuse device coupled between a second write line and the drain of the read enable device. A magnitude of current flowing in the bitline, when the read enable device is enabled for reading, is dependent both on (1) a voltage level applied to the first write line and anti-fuse device state and on (2) a voltage level applied to the second write line and fuse device state. Usages include in a memory array, such as for FPGA configuration memory. The bitcell can be used as a multi-time programmable element, or to store multiple bit values.

Abstract: Example embodiments disclosed herein relate to a method of transmitting an audio signal and also a method of receiving an audio signal. The method of transmitting the audio signal includes: receiving the audio signal including a plurality of frames having a left and right subframes containing audio data of a first number of bits; encoding the left and right subframes into a parity code of a second number of bits; generating serial data by combining the parity code and the audio data; and transmitting the serial data over an audio transmission media having a bandwidth of a third number of bits, a sum of the first number of bits and the second number of bits being below the third number of bits. The method of receiving the audio signal includes: receiving a serial signal combining a parity code; decoding the serial signal by calculating a syndrome based on the parity code; detecting an error by comparing the syndrome with the audio data; and generating a corrected audio signal by correcting the detected error.

Abstract: In one embodiment, memory circuitry includes an error-correction code (ECC) encoder, memory, and an ECC decoder. The ECC encoder performs encoding, based on an ECC algorithm having an algorithm size, on an algorithm-size segment of input user data to generate a corresponding subset of parity data for the segment of input user data. The memory has input user data and corresponding parity data written based on a write data size and stored user data and corresponding stored parity data read based on a read data size. The ECC decoder performs decoding, based on the ECC algorithm, on an algorithm-size segment of retrieved user data and a corresponding subset of retrieved parity data, wherein the algorithm size is smaller than the write data size or the read data size. The memory circuitry enables conventional SEC-DED algorithms to be used when the write and read data sizes are different.

Abstract: The discovery of a topology of a network with an unknown topology can enable the selection of a data path within the network, and the establishment of a data stream over the selected data path. Routing tables mapping originating nodes to input ports can be created based on the receipt of discovery messages generated by the originating nodes. A source node can select a data path between the source node and a sink node in order to establish a data stream using the routing tables. Data paths can be selected based on, for instance, routing table bandwidth information, latency information, and/or distance information. Data streams can be established over the selected data path, and each node can release any reserved output bandwidth determined to be unnecessary for the data stream.

Abstract: Various techniques are provided to efficiently implement user designs incorporating clock and/or data recovery circuitry and/or a deserializer in programmable logic devices (PLDs). In one example, a method includes receiving a serial data stream, measuring time periods between signal transitions in a serial data stream using at least one Grey code oscillator, and generating a recovered data signal corresponding to the serial data stream by, at least in part, comparing the measured time periods to one or more calibration time periods. In another example, a system includes a Grey code oscillator configured to increment a Grey code count between signal transitions in a serial data stream, and a Grey code converter configured to convert the Grey code count approximately at the signal transitions to a plurality of binary counts each corresponding to a time period between one or more signal transitions in the serial data stream.

Abstract: Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a programmable logic device (PLD) includes a plurality of programmable logic blocks (PLBs) and at least first and second logic cells within at least one of the PLBs, where each logic cell includes a lookup table (LUT) and associated mode logic configured to receive a LUT output signal from the LUT. The associated mode logic is configured to use a single physical signal output to provide a logic cell output signal corresponding to a selected logic function operational mode, ripple arithmetic operational mode, or extended logic function operational mode for each logic cell.

Abstract: Embodiments of the present disclosure relate to transmitting or receiving a media stream and associated control parameter over different physical channels. The transmitter transmits a media stream over a first physical channel and at least one associated control parameter along with a time parameter associated with a part of the media stream over a second physical channel. The associated control parameter along with the time parameter is sent before the media stream to the receiver. The receiver processes the media stream, by extracting the control parameter and time parameter associated with a part of the media stream, and at least applying the extracted control parameter to the part of the media stream.

Abstract: Systems, devices and methods for analog echo cancellation for high speed full duplex data transmissions, which include a first set of differential nodes to receive reception data and transmission data, a second set of differential nodes to receive the transmission data, and a subtraction circuit to receive data from the first set of differential nodes and data from the second set of differential nodes. The subtraction circuit includes a plurality of capacitors to receive data from each of the first and second sets differential nodes, and a termination circuit for providing DC termination voltage to subtract the data of the second set of differential nodes from the data of the first set of differential nodes to eliminate echo from the reception data received at the first set differential nodes.

Abstract: A disclosed wireless tunneling system tunnels communications between two processing apparatuses through a wireless link, while maintaining compliance of the communications between the two processing apparatuses with a wired communication protocol. In one embodiment, the wireless tunneling system includes two wireless tunneling apparatuses that communicate with each other through the wireless link. A local wireless tunneling apparatus is coupled to a local processing apparatus through a wired connection and a remote wireless tunneling apparatus is coupled to the remote processing apparatus through another wired connection. In one aspect, the local wireless tunneling apparatus predicts a state of the remote processing apparatus, and mirrors the predicted state of the remote processing apparatus.

Abstract: Maintaining synchronization of encryption processes at devices during transmission of encrypted data over a communication link is provided. Cipher link maintenance characters are sent from a source device to a sink device. A local cipher link maintenance character generated at the sink device for decrypting the encrypted data can be adjusted according to the cipher link maintenance character. After authentication, cipher link maintenance characters corresponding to units (e.g., frames) of the encrypted data are sent along with the units of the encrypted data. When a transmission error occurs during transmission of the encrypted data, cipher link maintenance characters can be used to correct the error in a local cipher link maintenance character generated at the sink device. Hence, even if the transmission error occurs in the communication link, the sink device can resolve the transmission error and maintain the synchronization of encryption processes at the source and sink devices.

Abstract: A disclosed wireless tunneling system determines a suitable configuration of a wireless tunneling apparatus for tunneling communications between two processing apparatuses through a wireless link. Responsive to determining the configuration of the wireless tunneling apparatus, the wireless tunneling system establishes a communication with another wireless tunneling apparatus through the wireless link, while maintaining compliance of the communications between the two processing apparatuses with a wired communication protocol. Moreover, the wireless tunneling apparatus can supply power to or source power from a processing apparatus coupled to the wireless tunneling apparatus through a wired cable.

Abstract: Disclosed wireless tunneling system includes two wireless tunneling apparatuses that communicate with each other through the wireless link. A local wireless tunneling apparatus is coupled to a local processing apparatus through a wired connection and a remote wireless tunneling apparatus is coupled to the remote processing apparatus through another wired connection. The two processing apparatuses bi-directionally communicate with each other through the wireless link using the two wireless tunneling apparatuses as if the two processing apparatuses were connected through a wired connection.