Abstract: Techniques are provided to reduce glitches at an output signal node when a device is switched to and from a low power operation mode. In one example, a method of operating a device includes providing power to operate a signal source of the device during a normal operation mode of the device. The method also includes passing an output signal from the signal source through a signal path to an output node during the normal operation mode. The method also includes receiving an operation mode signal to switch the device from the normal operation mode to a low power operation mode. The method also includes disabling the signal path to prevent glitches from appearing at the output node during the switch from the normal operation mode to the low power operation mode. The method also includes continuing providing power to the signal source until after the signal path is disabled.

Abstract: A core logic portion of a clocked digital circuit is switched to be powered by a standby mode power voltage lower than a normal mode power voltage when the circuit is switched into a low power standby mode (LPSM). The standby mode power voltage is too low relative to normal ground to deterministically drive a transition logic portion of the circuit. However, a special ground bus (GNDx) is provided in the transition logic portion and that special ground bus (GNDx) is pulled down to a negative voltage below normal ground when the circuit is switched into the low power standby mode (LPSM).

Abstract: Various techniques are disclosed to identify composite wires from segmented wires of a programmable logic device (PLD). In one example, a method includes associating segmented wires of the PLD with a plurality of wire index values based on connections identified by interface templates. The method further includes identifying a plurality of composite wires according to the wire index values. Each composite wire comprises a set of the segmented wires associated with a corresponding one of the wire index values. The composite wires are adapted to interconnect programmable logic blocks of the PLD.

Abstract: In certain embodiments of the invention, a serializer has (a) an initial, transfer stage that transfers incoming parallel data from a relatively slow timing domain to a relatively fast timing domain and (b) a final, serializing stage that converts the parallel data into serialized data. Between the transfer stage and the serializing stage is an update stage that (i) buffers data between the initial and final stages and (ii) can be used to toggle the serializer between an N?1 operating mode (that serializes (N?1) bits of parallel data) and an N+1 operating mode (that serializes (N+1) bits of parallel data) to achieve a net N:1 gearing ratio where N is an odd integer. The serializer can be configurable to support other gearing ratios as well.

Abstract: Various techniques are provided for synchronizing serial data signals received by electronic systems or devices such as programmable logic devices (PLDs). In one example, a method of synchronizing data includes receiving a serial data signal at a device. The serial data signal operates independently of the device. The method also includes oversampling the serial data signal to provide a plurality of samples distributed over bit periods of the serial data signal. The method further includes filtering the samples to correct errors in the samples. In addition, the method includes extracting a plurality of data bit values from the samples under the control of a clock signal associated with the device without adjusting a frequency of the clock signal. Each data bit value is associated with one of the bit periods of the serial data signal.

Abstract: A method of providing a clock signal for an embodiment includes performing a calibration for a closed loop control system to determine a control signal value that provides a desired tuning of the closed loop control system. The control signal value is stored and provided to a delay circuit, wherein a delay range and a delay step size of the delay circuit is based on the control signal value. A delay select control signal is provided to the delay circuit to select a specific delay within the delay range.

Abstract: In one embodiment, a configurable delay element has three stages. The first stage has an 8-buffer first delay chain and an (8×1) first mux that selects one of the eight first-delay-chain outputs. The second stage has a 24-buffer second delay chain connected to receive the first-mux output and organized into three 8-buffer sub-chains and a (4×1) second mux that selects one of the four second-delay-chain outputs. The third stage has a 96-buffer third delay chain connected to receive the second-mux output and organized into three 32-buffer sub-chains and a (4×1) third mux that selects one of the four third-delay-chain outputs as the delay-element output signal. A delay-element controller provides glitch-less updates to the signal used to control the delay-element muxes by timing those updates to occur when all delay-element buffers have the same state. The controller bases the update timing on the delay-element output signal.

Abstract: In one embodiment, a combined VGA-and-equalizer (VGA-EQ) circuit for a communication link includes a current-mode logic (“CML”) amplifier with an inductive load circuit. The CML amplifier has a gain control terminal and is operable to amplify, with an adjustable gain, a signal received at an input terminal and provide the amplified signal at an output terminal. The CML amplifier has a first gain at frequencies below a predetermined frequency value and a second gain at frequencies in a predetermined frequency range above the predetermined frequency value, wherein the second gain is higher than the first gain. The higher second gain of the VGA-EQ circuit causes a reduction in inter-symbol interference in a signal received by the receiver.

Abstract: In one embodiment, a circuit such as a comparator circuit includes a differential stage adapted to receive a differential input signal and first and second diodes coupled to the differential stage. The first and second diodes are adapted to selectively switch on and off to provide a differential output signal at first and second differential output nodes in response to the differential input signal. The circuit may include an output stage coupled to the first and second diodes at the first and second differential output nodes, with the output stage adapted to convert the differential output signal to a single ended output signal. The circuit may also include a current source adapted to selectively provide a reference current to the first or second diode in an off state to reduce voltage swing of the first or second diode between the off and an on state.

Abstract: A mapping circuit is provided for mapping first data words into frames of second data words, wherein the first and second data words are of different length. In addition, a de-mapping circuit is provided for de-mapping the frames of second data words into the first data words. The mapping and de-mapping is responsive to address signals that may be stored in a memory such that a desired mapping or de-mapping corresponds to a particular programming of the memory. In this fashion, the mapping and de-mapping is in-system reconfigurable.

Abstract: In an exemplary decision-feedback equalizer (DFE) of a serializer/deserializer (SerDes) receiver, a single current mirror array is shared by multiple current digital-to-analog converter (IDAC) functions. The DFE has an initial amplifier stage that applies an initial coefficient COEFF0 to an input data signal and a number of (e.g., five) additional amplifier stages that apply additional coefficients (e.g., COEFF1-COEFF5) to different delayed versions of the recovered output data stream. The outputs of the initial and multiple additional amplifier stages are summed to generate an equalized data signal that is applied to a clock-and-data recovery (CDR) circuit. Due to certain characteristics of the equalizer function, the multiple additional amplifier stages can be implemented using a single shared current mirror array, which save significant amounts of chip area compared to conventional implementations in which each additional amplifier stage has its own dedicated current mirror array.

Abstract: In one embodiment, a programmable logic device (PLD) includes a programmable fabric and hard logic coupled to the programmable fabric. The hard logic includes a timing measurement circuit adapted to measure latency of a data path between first and second points in the programmable logic device, such as the latency of a data path through a link interface configured within the programmable fabric.

Abstract: Systems and methods are disclosed herein to provide channel-to-channel skew control in accordance with one or more embodiments of the present invention. For example in accordance with an embodiment, a method of adjusting skew between first and second channels includes receiving a first channel output signal and a second channel output signal from the first and second channels, respectively; detecting a phase difference between the first channel output signal and the second channel output signal; and controlling, based on the detected phase difference, a signal delay within at least the first channel or the second channel to reduce skew between the first channel output signal and the second channel output signal.

Abstract: In one embodiment, a clock distribution chip includes a clock input adapted to receive an input clock signal, clock dividers each adapted to receive a clock signal based on the first input clock signal and to generate a divided clock signal, and programmable clock outputs adapted to provide output clock signals. The clock outputs are configurable to support a number of signaling standards. A programmable switch fabric is coupled between the clock dividers and the clock outputs and is configurable to provide the divided clock signals to the clock outputs.

Abstract: Techniques are provided for reducing signal congestion in programmable logic devices (PLDs). In one example, a computer-implemented method of reducing signal congestion in a configuration of a PLD includes mapping a plurality of circuit components of a circuit design to a plurality of components of the PLD, wherein each of the mapped PLD components is associated with one of a plurality of regions of the PLD and with one or more unique signal paths entering the PLD region. The method also includes determining a cost value for each PLD region based at least in part on the number of unique signal paths entering the PLD region from other PLD regions. The method also includes selecting one of the PLD components to move from a first one of the PLD regions to a second one of the PLD regions. The method also includes updating the cost values associated with the first and second PLD regions based on a change in the number of unique signal paths entering the first and second PLD regions.

Abstract: In one embodiment, a clock distribution chip includes a first clock input adapted to receive a first single-ended input clock signal, a second clock input adapted to receive a second single-ended input clock signal, and input buffer circuitry coupled to the first and second clock inputs. The input buffer circuitry is adapted to select an input clock signal among the first single-ended input clock signal, the second single-ended input clock signal, and a differential input clock signal derived from the first and second single-ended input clock signals. A phase-locked loop (PLL) is adapted to receive an input clock signal selected by the input buffer circuitry and to generate a PLL clock signal based on the selected input clock signal. A clock output provides an output clock signal based on the PLL clock signal.

Abstract: In one embodiment, a method of verifying a programming operation of a programmable logic device includes storing in non-volatile memory within the programmable logic device configuration data and a pre-calculated code value based on the configuration data. The method further includes transferring the configuration data from non-volatile memory to configuration memory within the programmable logic device; calculating a code value based on the configuration data transferred from the non-volatile memory to the configuration memory; and comparing the calculated code value to the pre-calculated code value.

Abstract: A computer-implemented method of referencing wires of a routing graph of a programmable logic device (PLD). In one embodiment, the method includes mapping the first routing graph wire to a master wire; mapping the first master wire to master switch; identifying a segmented wire connected to the master switch; mapping the identified segmented wire to a second master wire; and mapping the second master wire to the second routing graph wire.

Abstract: In one embodiment of the invention, a programmable logic device (PLD) includes logic blocks, registers corresponding to the logic blocks, and configuration memory adapted to store configuration data for configuring the PLD. Also included in the PLD is a general routing network having a plurality of routing wires and a clock distribution network having a plurality of routing wires. At least one clock signal path is provided within the PLD from a clock source to one of the registers via a routing wire of the clock distribution network and a routing wire of the general routing network.

Abstract: Various techniques are described to provide an internally triggered reconfiguration of a programmable logic device (PLD). In one example, a PLD includes configuration memory adapted to store first configuration data to configure the PLD for its intended function. The PLD also includes a bus interface adapted to interface with configuration data storage memory. The PLD further includes user logic configured by the first configuration data and adapted to provide a reconfiguration signal to trigger a reconfiguration of the PLD. In addition, the PLD includes a bus interface controller responsive to the reconfiguration signal for loading second configuration data from the configuration data storage memory via the bus interface.