Abstract: In one embodiment, a programmable logic device includes a plurality of configuration cells that store configuration data, wherein the programmable logic device is adapted to provide soft error upset (SEU) protection for the configuration cells that are reprogrammable. The programmable logic device may further include or alternatively provide hard coding and/or hard encoding of the configuration cells.

Abstract: Various techniques are provided for determining interface characteristics of external devices. In one example, a method of configuring a programmable logic device (PLD) with configuration data stored in one or more external memory devices includes reading by the PLD an interface setup command in a bitstream from an external memory device through a configuration port of the PLD while operating the configuration port in accordance with a first set of interface characteristics. The method also includes adjusting by the PLD the configuration port to operate in accordance with a second set of interface characteristics identified by the interface setup command. The method also includes reading by the PLD configuration data in the bitstream from the external memory device through the configuration port while operating the configuration port in accordance with the second set of interface characteristics. The method also includes programming a configuration memory of the PLD with the configuration data.

Abstract: A flexible delay cell architecture and related methods are provided that may be used, for example, with input/output (I/O) blocks of a programmable logic device (PLD). In one implementation, a PLD includes a delay cell comprising a plurality of delay elements. The delay elements are adapted to delay an input signal to provide an output signal according to a delay setting corresponding to a number of the delay elements. The PLD also includes a register adapted to store the delay setting. The PLD further includes an edge monitor adapted to signal whether an edge transition of the output signal has occurred during a time window. In addition, the PLD includes logic adapted to adjust the delay setting stored by the register in response to the edge monitor signaling the edge transition.

Abstract: In one embodiment of the invention, a receiver has two mux circuits, two receiver circuits, and a mixer. The muxes select first and second input signals for the receiver circuits. A p-type transistor in a transmission gate in each mux is connected (i) at its channel nodes between a pad and the mux output and (ii) to receive a control signal at its gate node. Control circuitry for the p-type transistor implements a threshold reduction filter that ensures that a maximum voltage level at the mux output is at least a threshold below the mux's power supply voltage. Based on first and second input signals, the first receiver circuit generates first and second intermediate signals, and the second receiver circuit generates third and fourth intermediate signals. The mixer circuit combines the intermediate signals to generate first and second output signals, wherein the first and second receiver circuits effectively operate over different ranges of common-mode voltages.

Abstract: In embodiment of the invention, a programmable logic device includes configuration memory adapted to be programmed with configuration data and a plurality of programmable fuses adapted to store a security key for use with configuration data. The security key includes a plurality of data bit values, wherein each data bit value of the security key is associated with a subset of a least three fuses each storing a bit. Each of a plurality of decoders is adapted to retrieve a data bit value of the security key by providing the bit value stored by a majority of the fuses of the associated subset as the data bit value of the security key.

Abstract: An integrated circuit includes, in accordance with an embodiment of the present invention, a data port, a system bus for transferring information to and from the data port, and a plurality of SERDES channels. A plurality of registers associated with the plurality of SERDES channels may be written to via the system bus on an individual, group, or global basis to provide communication settings for the SERDES channels.

Abstract: In one example, a method of detecting timing errors in a configuration of a programmable logic device (PLD) includes performing a timing analysis on the PLD configuration. The PLD configuration is adapted to configure the PLD to perform a data transfer between a first clock domain synchronized by a first clock signal received by a double data rate (DDR) block of the PLD configuration and a second clock domain synchronized by a second clock signal received by the DDR block. The method includes calculating a slack value associated with the data transfer using a first delay associated with the first clock signal, a second delay associated with the second clock signal, and a time constraint associated with the data transfer. The first delay and the second delay are provided by the timing analysis. The method includes determining whether the PLD configuration satisfies the time constraint based on the slack value.

Abstract: In one embodiment of the invention, a method of generating a compressed configuration bitstream for a programmable logic device comprises encoding the most-prevalent data word within the configuration data of the bitstream into a codeword of a first type; encoding a set of more-prevalent data words within the configuration data into codewords of a second type; and including in the compressed bitstream at least some of the data words that are members of the set of more-prevalent data words. The included data words, when received by the programmable logic device, are adapted to be identified by the device as members of the set of more-prevalent data words. The included data words are stored for selection by the device when a codeword of the second type representing an included data word is received by the device.

Abstract: In one embodiment, an integrated circuit such as an FPGA includes one or more data I/O blocks, one or more FIFOs, and a FIFO controller. At least one data I/O block receives an incoming bit stream from an external device. At least one FIFO is connected to receive a corresponding incoming bit stream from a corresponding data I/O block. The FIFO controller controls operations of the one or more FIFOs, such that (i) bits from the corresponding data I/O block are written into the at least one FIFO using a FIFO write clock that is based on an incoming clock signal and (ii) bits are read out from the at least one FIFO using a FIFO read clock that is based on a local reference clock signal.

Abstract: Various techniques are described to identify composite wires from segmented wires of a programmable logic device (PLD). In one example, a method includes identifying a plurality of interface templates corresponding to tiles of the PLD. The PLD comprises a plurality of segmented wires arranged in a plurality of tiles. Each interface template corresponds to at least two adjacent tiles of the PLD and identifies connections between segmented wires of the corresponding adjacent tiles. The method also includes associating the segmented wires of the PLD with a plurality of wire index values based on the connections identified by the interface templates. The method further includes identifying a plurality of composite wires according to the wire index values. Each composite wire comprises a set of the segmented wires associated with a corresponding one of the wire index values. The composite wires are adapted to interconnect programmable logic blocks of the PLD.

Abstract: Within a programmable logic device, a multi-data rate SDRAM interface such as a DDR SDRAM interface includes in one embodiment a DQS clock tree, a slave delay circuit, and a delay-locked loop (DLL). The slave delay circuit is adapted to shift the phase of the DQS signal relative to the phase of data to provide a phase-shifted DQS signal to the DQS clock tree, and the DLL is adapted to control the slave delay circuit. The DLL includes a delay line comprising a plurality of instantiations of the slave delay circuit and a plurality of facsimiles of the DQS clock tree.

Abstract: Systems and methods provide I/O signal placement algorithms, such as for a programmable logic device. For example, a performing input/output (I/O) signal placement to pins of an electronic device, in accordance with an embodiment, includes placing all pre-assigned I/O signals to their assigned pin locations; placing unassigned I/O signals to initial I/O pin locations; and performing a simulated annealing for the I/O signals placed at initial I/O pin locations, wherein the simulated annealing accounts for simultaneous switching output (SSO) noise requirements.

Abstract: In one embodiment, a programmable logic device (PLD) includes a slave port and a master port. The slave port can receive a configuration data bitstream and a slave clock signal from a master port of a first external device. The master port can provide the configuration data bitstream and a master clock signal from the PLD to a slave port of a second external device. An interface block in the PLD can pass the configuration data bitstream from the slave port through the PLD to the master port. In another embodiment, a PLD includes a slave serial peripheral interface (SPI) port and configuration memory. The slave SPI port can receive a configuration data bitstream and a slave clock signal from a master SPI port of an external device. The configuration memory stores the received bitstream for configuring the PLD.

Abstract: In one embodiment, a method is provided for measuring a dynamic phase offset between a PLL's input clock and the PLL's feedback input clock, wherein the input clock is spread spectrum modulated in a spread spectrum mode and is not modulated in a static mode. The method includes: in the spread spectrum mode, measuring phase jitter between the input clock and the feedback input clock to form a spread spectrum phase jitter measurement; in the static mode, measuring phase jitter between the input clock and the feedback input clock to form a static phase jitter measurement; and comparing the spread spectrum phase jitter measurement to the static phase jitter measurement to determine the dynamic phase offset.

Abstract: Systems and methods provide techniques to support design specific testing for programmable logic devices in accordance with one or more embodiments. For example in one embodiment, a method of generating configuration data for a programmable logic device includes mapping a design for the programmable logic device, wherein the mapped design incorporates scan test logic; placing and routing the mapped design; and generating configuration data based on the mapped design, wherein the incorporated scan test logic is disabled and not selectable within the programmable logic device configured with the configuration data. The method may further include generating a second configuration data based on the mapped design, wherein the incorporated scan test logic is enabled and selectable within the programmable logic device configured with the second configuration data.

Abstract: In one embodiment, a programmable logic device includes a plurality of configuration memory cells and at least one spare configuration memory cell adapted to store configuration data for a memory cell identified within the plurality of configuration memory cells (e.g., identified as a defective memory cell). An address shift register within the device is adapted to provide programming signals to the plurality of configuration memory cells via wordlines. A data shift register within the device is adapted to provide configuration data to the plurality of configuration memory cells via bitlines. The data shift register is further adapted to provide configuration data from the spare configuration memory cell to the identified configuration memory cell.

Abstract: A method of programming a programmable logic device (PLD), in accordance with an embodiment, includes receiving trigger unit information of a logic analyzer via a software interface for monitoring internal PLD signals and providing trigger unit output signals based on the internal PLD signals for the corresponding trigger units; and receiving trigger expression information of the logic analyzer via the software interface as a text string of logic operators and operands, wherein the operands represent the trigger unit output signals. The method may further include generating configuration data based on the trigger unit information and the trigger expression information; and providing the configuration data to the PLD, wherein a trigger expression based on the trigger expression information is stored within memory of the PLD.

Abstract: In one embodiment, a programmable logic device includes a plurality of configuration cells that store configuration data, wherein the programmable logic device is adapted to provide soft error upset (SEU) protection for the configuration cells that are reprogrammable. The programmable logic device may further include or alternatively provide hard coding and/or hard encoding of the configuration cells.

Abstract: In accordance with an embodiment of the present invention, a programmable logic device (PLD, such as a field programmable gate array (FPGA)) includes a plurality of input/output blocks adapted to precondition registers within the programmable logic device with desired signal values prior to release of control of the input/output blocks to user-defined logic provided by a reconfiguration.

Abstract: Various serial interface implementations and related methods are provided for establishing serial data links with programmable logic devices (PLDs). In one example, a PLD includes a plurality of programmable logic blocks adapted to be programmed to configure the PLD for its intended function. The PLD also includes a serial interface comprising a transmit port, a microcontroller, a transmit register, and transmit logic. The microcontroller is adapted to adjust pre-emphasis settings associated with the transmit port to tune a serial data link between the PLD and an external device. The transmit register is adapted to receive a data signal from the programmable logic blocks. The data signal comprises transmit data to be provided over the serial data link through the transmit port. The transmit logic is adapted to prepare a serial signal for transmission from the transmit port over the serial data link. The serial signal comprises the transmit data.