Abstract: Various techniques are provided for routing signals to pins of components of programmable logic devices (PLDs). In one example, a computer-implemented method of routing signals in a PLD includes routing a plurality of signals to pins of a component of the PLD. At least two of the signals are routed to a same pin. The method also includes, for each of the signals routed to the same pin, determining a cost value associated with each of two or more pins. the method also includes, for each of the signals routed to the same pin, rerouting the signal to one of the two or more pins having the lowest cost value. The method also includes repeating the determining a cost value and the rerouting until no more than one signal is routed to a pin.

Abstract: A programmable logic device, in accordance with one embodiment, includes a plurality of configuration memory cells, wherein at least one configuration memory cell is adapted to function as random access memory. Read/write circuitry writes to and reads from a corresponding first port of the configuration memory cells, including reading from the at least one configuration memory cell adapted to function as random access memory. Soft error detection logic checks for an error in data values stored by the plurality of configuration memory cells, including the at least one configuration memory cell adapted to function as random access memory. The soft error detection logic, for example, may thus be tested by changing a data value stored in the at least one configuration memory cell.

Abstract: In one embodiment, an integrated circuit includes a flash memory array with at least first and second subarrays, or sectors, of memory cells. The subarrays have a set of shared bitlines and separate sets of word lines. A bitline driver circuit is coupled to the set of shared bitlines, a first row driver circuit is coupled to the set of word lines of the first subarray, and a second row driver circuit is coupled to the set of word lines of the second subarray. The first and second row driver circuits are operable to enable the memory cells of the first subarray to be erased independently of the memory cells of the second subarray. The two row driver circuits are further operable to enable the memory cells of the second subarray to be erased independently of the memory cells of the first subarray.

Abstract: In one embodiment of the invention, a programmable logic device includes configuration memory and a controller. The controller can read a first bitstream from a first memory block of non-volatile memory and detect whether the first bitstream contains a valid preamble as the first bitstream is read from the non-volatile memory and before configuration data in the first bitstream is programmed into the volatile configuration memory. If a valid preamble is detected in the first bitstream, the controller programs the configuration memory with configuration data in the first bitstream. If a valid preamble is not detected in the first bitstream, the controller reads a second bitstream from a second memory block of the non-volatile memory.

Abstract: In one embodiment, a method of converting an uncompressed bitstream into a compressed bitstream for a programmable logic device (PLD) is disclosed. The method includes embedding a first data frame from the uncompressed bitstream into the compressed bitstream, wherein the first data frame comprises a first data set; embedding a first instruction into the compressed bitstream to load the first data frame into a first row of configuration memory of the PLD at an address associated with the first data frame; identifying a second data frame in the uncompressed bitstream, wherein the second data frame comprises the first data set; and embedding a second instruction into the compressed bitstream to load the first data frame into a second row of the configuration memory at an address associated with the second data frame.

Abstract: In one example, a comparator circuit includes a differential stage adapted to receive a differential input signal. The comparator circuit includes first and second diodes coupled to the differential stage. The first and second diodes are adapted to selectively switch on and off to provide a differential output signal at first and second differential output nodes in response to the differential input signal. The comparator circuit includes a current steering circuit adapted to selectively provide a reference current from a current source to the first or second diode in an off state to reduce a voltage swing of the first or second diode between the off state and an on state. The comparator circuit includes an output stage coupled to the first and second diodes at the first and second differential output nodes. The output stage is adapted to convert the differential output signal to a single ended output signal.

Abstract: A programmable logic device (PLD) is provided that includes: a plurality of programmable logic blocks, the plurality of programmable logic blocks being associated with a first configuration data shift register operable to shift in configuration data for the plurality of programmable logic blocks; a plurality of input/output (I/O cells), each I/O cell associating with a corresponding set of I/O configuration memory cells; and a plurality of boundary scan cells corresponding to the plurality of I/O cells, each boundary scan being configurable to form a second data shift register for the I/O configuration memory cells.

Abstract: A method of recovering from a soft error within configuration data stored in a configured programmable logic device. The method includes repeatedly processing the configuration data stored within configuration memory of the device using an error-detection algorithm to generate a checksum. The generated checksum is compared with a previously generated checksum to detect if a soft error exists in the configuration data. If a soft error is detected, the programmable logic device initiates a reconfiguration of the configuration memory. The configuration memory is then reconfigured with the configuration data while preventing the programmable logic device from responding to the reconfiguration as though the reconfiguration was an initial configuration of the device. An embodiment of a programmable logic device designed for practicing the method is also disclosed.

Abstract: Various techniques are provided for estimating signal congestion in a programmable logic device (PLD). In one example, a computer-implemented method of estimating signal congestion in routing resources of a PLD is provided. The routing resources comprise a plurality of nodes and a plurality of wires which may be selectively interconnected to provide a plurality of signal paths through the routing resources of the PLD. The method includes determining a plurality of wire congestion values. Each of the wire congestion values identifies a relative likelihood of a corresponding one of the wires being used to provide the signal paths in comparison with the other wires. The method also includes selecting a region of the routing resources. The method further includes determining a congestion density estimate for the region using the wire congestion values associated with the wires of the region.

Abstract: In one embodiment, an integrated circuit includes a substrate having high voltage transistor regions and low voltage transistor regions. The substrate includes a first trench between and adjacent to the high voltage transistor regions, a second trench between and adjacent to the low voltage transistor regions, and a third trench between the first and second trenches and between and adjacent to a high voltage transistor region and a low voltage transistor region. A thicker silicon dioxide layer lines the first trench and a first portion of the third trench adjacent to a high voltage transistor region. A thinner silicon dioxide layer lines the second trench and a second portion of the third trench adjacent to a low voltage transistor region.

Abstract: A method of manufacturing an integrated circuit includes etching a substrate to create simultaneously a first trench between high voltage transistor regions of the substrate and a second trench between low voltage regions of the substrate. The substrate is then oxidized to form a silicon dioxide layer lining the first and second trenches, the layer having a first thickness. A silicon nitride layer is deposited on the silicon dioxide layer in the first and second trenches. The silicon nitride layer is then etched from the first trench but not from the second trench, thereby exposing the silicon layer in the first trench but not the second trench. The exposed silicon dioxide layer in the first trench is oxidized to increase the thickness of the silicon dioxide layer to a second thickness greater than the first thickness of the unexposed silicon dioxide layer in the second trench. The first and second trenches are then filled with a dielectric material.

Abstract: In one example, a method of tuning an oscillator of a phase-locked loop (PLL) circuit includes adjusting a coarse control signal to select one of a plurality of frequency tuning curves of the oscillator. The method includes adjusting a fine control signal to select a position on the selected frequency tuning curve. A frequency of the oscillator is determined by the coarse control signal and the fine control signal. The method includes attempting to detect a lock between a feedback signal and a reference signal. A frequency of the feedback signal is determined by the frequency of the oscillator. The method includes comparing the fine control signal to a reference value if the lock is detected. The method includes adjusting the coarse control signal to select a different one of the frequency tuning curves if the selected position on the selected frequency tuning curve is outside a desired tuning range.

Abstract: In one embodiment, a programmable logic device includes a plurality of logic blocks; a plurality of input/output blocks; volatile configuration memory adapted to store configuration data for configuration of the logic blocks and input/output blocks; embedded block RAM adapted to store user data; flash memory having at least a first partition and a second partition; and a data port adapted to provide external device access to the first partition of the non-volatile memory. The flash memory is adapted to store within the first partition user data from the data port and is further adapted to store within the second partition user data from the embedded block RAM.

Abstract: In one embodiment of the invention, an integrated circuit such as a programmable logic device includes volatile memory, nonvolatile memory, and a data shift register for reading data from the nonvolatile memory and for reading data from and writing data to the volatile memory. A built in self test (BIST) circuit is operable to test the nonvolatile memory without the data shift register reading data from the nonvolatile memory. The BIST circuit may include a finite state machine for performing at least one of the following tests on the nonvolatile memory: bulk erase, bulk program; margin bulk program; and/or margin bulk erase. A memory controller responsive to the finite state machine is operable to write data to and read data from the nonvolatile memory during testing of the nonvolatile memory.

Abstract: A programmable logic device (PLD), is provided that includes: a plurality of SERDES channels; a programmable logic fabric configured to implement an interface for a standardized cellular base station system; wherein the interface receives data words from the SERDES channels and transmits data words to the SERDES channels, and wherein a standard corresponding to the standardized base station system restricts a latency with regard to flow of the data words through the interface, the data words being arranged into frames; and a timing measurement circuit configured to measure a delay between a detection of a first timing point in the frames at first location in the PLD with respect to the interface and a detection of a second timing point in the frames at a second location in the PLD with respect to the interface.

Abstract: Various techniques are provided to compress and decompress configuration data for use with programmable logic devices (PLDs). In one example, a method includes embedding a first data frame comprising a data set from an uncompressed bitstream into a compressed bitstream. The method also includes embedding a first instruction to instruct a PLD to load the first data frame into a data shift register, embedding a second instruction to instruct the PLD to load a first address associated with the first data frame into an address shift register, and embedding a third instruction to instruct the PLD to load the first data frame from the data shift register into a first row of a configuration memory corresponding to the first address. The method further includes identifying a second data frame comprising the data set in the uncompressed bitstream, and embedding fourth and fifth instructions in place of the second data frame.

Abstract: A high voltage transistor exhibiting an improved breakdown voltage and related methods are provided. For example, a method of manufacturing an integrated circuit includes etching a poly silicon layer to provide a gate stacked above a floating gate of a flash memory cell. A source and a drain of the flash memory cell are implanted in a substrate. The poly silicon layer is etched to provide a gate of a high voltage transistor. Lightly doped drain (LDD) implants are provided in source/drain regions of the high voltage transistor in the substrate. An annealing operation is performed on the integrated circuit, wherein the annealing causes each of the LDD implants to form a graded junction in relation to a channel in the substrate between the LDD regions, and further causes sidewalls to oxidize on the gates of the flash memory cell and on the gate of the high voltage transistor.

Abstract: Systems and methods provide improved techniques directed to simultaneous switching output (SSO) noise, which for example may be applied during the programmable logic device design process. For example in accordance with an embodiment, a method of structuring simultaneous switching output (SSO) noise data for an electronic device includes collecting hardware data on SSO noise conditions; generating additional data on SSO noise conditions based on the hardware data; and structuring the hardware data and the additional data to form data tables for SSO noise calculations.

Abstract: Various techniques for referencing components of a programmable logic device (PLD) are provided. In one example, a method of referencing wires of a routing graph of a PLD is provided. The routing graph comprises a plurality of routing graph wires and a plurality of routing graph switches corresponding to components of the PLD. The method includes maintaining a plurality of master tiles comprising a plurality of master wires and a plurality of master switches corresponding to the routing graph wires and the routing graph switches, respectively. The method also includes identifying a first one of the routing graph wires. The method further includes mapping the first routing graph wire to a second one of the routing graph wires using at least one of the master wires.

Abstract: Systems and methods provide register data retention techniques for a programmable logic device in accordance with one or more embodiments of the present invention. For example, in one embodiment, a programmable logic device includes a plurality of logic blocks adapted to generate user data during operation of the programmable logic device; a plurality of registers adapted to store the user data during a reprogramming operation of the programmable logic device; and configurable routing resources adapted to provide a programmed data path between the logic blocks and the registers.