Abstract: A Time Dependent Dielectric Breakdown (TDDB) test pattern circuit, which can reduce testing time and statistically improve a precision of measurement as well as a method for testing the test pattern circuit are discussed. Typically, a test pattern circuit includes in plurality of unit test patterns. Each unit test pattern includes a capacitor connected to a stress voltage. The stress voltage is applied to the capacitor and the current flowing from the capacitor is measured over time. The dielectric in the capacitor breaks down over time and at a certain point, the current from the capacitor changes suddenly. Unfortunately, the convention test pattern circuit requires serial testing of each unit cell, and therefore, the measuring time is significant when there are many unit cells involved. The circuit allows for the measurements to take place simultaneously for all unit cells within the test pattern circuit.

Abstract: A Time Dependent Dielectric Breakdown (TDDB) test pattern circuit, which can reduce testing time and statistically improve a precision of measurement as well as a method for testing the test pattern circuit are discussed. Typically, a test pattern circuit includes in plurality of unit test patterns. Each unit test pattern includes a capacitor connected to a stress voltage. The stress voltage is applied to the capacitor and the current flowing from the capacitor is measured over time. The dielectric in the capacitor breaks down over time and at a certain point, the current from the capacitor changes suddenly. Unfortunately, the convention test pattern circuit requires serial testing of each unit cell, and therefore, the measuring time is significant when there are many unit cells involved. The circuit allows for the measurements to take place simultaneously for all unit cells within the test pattern circuit.

Abstract: A method for forming an isolation layer of a semiconductor device which is capable of improving isolation characteristics of a highly integrated semiconductor device. The method includes the steps of forming a first insulating layer on a substrate; forming both a first recess in the first isolation region and a plurality of second recesses in the second isolation region by only once applying a photolithography process to the first insulating layer; forming a third recess, which is deeper than the first recess, in the center area of the first recess in the first isolation region; and filling the first, second, third recesses with insulating materials or a thermal oxide layer. In addition, in the semiconductor device in which the isolation region has different widths, the first isolation region which is relatively narrower in width than the second isolation region has a deeper recess than the second isolation region.

Abstract: An instruction decoding unit in a microcomputer is disclosed having an instruction word capable of being selected by a user to conveniently produce application software while maintaining security. The decoding unit in a microcomputer includes an instruction register for storing instructions fetched from a memory, an instruction decoder for decoding instruction codes of the instructions stored in the instruction register and for designating micro-instructions to be executed, a micro-ROM for outputting a series of the micro-instructions designated by the instruction decoder, and a user instruction selector for selecting or changing the micro-instructions of the micro-ROM in response to user's selection so as to change the operation of an instruction word.

Abstract: A Time Dependent Dielectric Breakdown (TDDB) test pattern circuit, which can reduce testing time and statistically improve a precision of measurement as well as a method for testing the test pattern circuit are discussed. Typically, a test pattern circuit includes in plurality of unit test patterns. Each unit test pattern includes a capacitor connected to a stress voltage. The stress voltage is applied to the capacitor and the current flowing from the capacitor is measured over time. The dielectric in the capacitor breaks down over time and at a certain point, the current from the capacitor changes suddenly. Unfortunately, the convention test pattern circuit requires serial testing of each unit cell, and therefore, the measuring time is significant when there are many unit cells involved. The circuit allows for the measurements to take place simultaneously for all unit cells within the test pattern circuit.

Abstract: The present invention relates to a diffusion barrier layer for a semiconductor device and fabrication method thereof. The diffusion barrier layer according to the present invention is fabricated by forming a diffusion barrier layer containing a refractory metal material and an insulating material on an insulating layer and in a contact hole, wherein the insulating layer being partially etched to form the contact hole, is formed on a semiconductor substrate; and annealing the diffusion barrier layer. Therefore, an object of the present invention is to provide a diffusion barrier layer for a semiconductor device, which is of an amorphous or microcrystalline state and thermodynamically stable even at a high temperature since an insulating material is bonded to a refractory metal material in the diffusion barrier layer.

Abstract: A Time Dependent Dielectric Breakdown (TDDB) test pattern circuit, which can reduce testing time and statistically improve a precision of measurement as well as a method for testing the test pattern circuit are discussed. Typically, a test pattern circuit includes in plurality of unit test patterns. Each unit test pattern includes a capacitor connected to a stress voltage. The stress voltage is applied to the capacitor and the current flowing from the capacitor is measured over time. The dielectric in the capacitor breaks down over time and at a certain point, the current from the capacitor changes suddenly. Unfortunately, the convention test pattern circuit requires serial testing of each unit cell, and therefore, the measuring time is significant when there are many unit cells involved. The circuit allows for the measurements to take place simultaneously for all unit cells within the test pattern circuit.

Abstract: Device and method for managing a snap shot in a USB camera, the device including a camera for taking, and digitizing an image, and providing the image through an end point exclusive for an image, an interface unit for inserting either a frame sync pattern between frames of image data provided through an end point exclusive for an image or a snap shot sync pattern instead of the frame sync pattern in a snap shot mode, and a USB host for displaying an image data provided from the interface unit on a monitor in the USB host or forwarding for a picture communication, the method including the steps of (1) determining turning on/off of a snap shot button on the camera, (2) according to a result of the determination, either inserting a frame sync pattern between frames of image data and providing to the USB host, or inserting a snap shot sync pattern instead of the frame sync pattern and providing to the USB host, and (3) either displaying an image data having the frame sync pattern or the snap shot sync pattern ins

Abstract: Memory of a multilevel quantum dot structure and a method for fabricating the same, is disclosed, the method including the steps of (1) forming a first insulating layer on a substrate, (2) repeating formation of a conductive layer and a second insulating layer on the first insulating layer at least once, and (3) agglomerating each of the conductive layers to form quantized dot layers.

Abstract: A semiconductor wafer cleaning apparatus comprises an outer tank, a cleaning tank provided within the outer tank, a wafer carrier provided within the cleaning tank, a plurality of jet nozzles directed toward the wafer carrier, a main pipe connected to the jet nozzles, a circulating pump connected to the main pipe and the outer tank for circulating a cleansing solution from the outer tank, through the main pipe, the jet nozzles, and the cleaning tank, and a filter for filtering the circulated cleansing solution.

Abstract: Provided with a solid state image sensor, which is adapted to simplify the process with enhancement of the morphology of the device and has photo-diodes formed on a semiconductor substrate, and transfer gates disposed around the photo-diodes to transfer signal charges generated from the photo-diodes, the solid state image sensor including: an insulating layer forming on the whole surface of the semiconductor substrate and having a contact hole exposing a defined portion of the transfer gates; a metal line formed to include the inside of the contact hole; and a light-shielding layer formed in the same layer with the metal line without overlapping the upper parts of the photo-diodes.

Abstract: Mask ROM cell and method of fabricating the same, is disclosed, including a semiconductor substrate of a first conductivity type, a plurality of impurity diffusion regions of a second conductivity type, formed in the semiconductor substrate in one direction, having a predetermined distance therebetween, an insulating layer formed on a portion of the semiconductor substrate, corresponding to each impurity diffusion region, a gate insulating layer formed on the semiconductor substrate, and a plurality of conductive lines formed on the gate insulating layer and insulating layer in a predetermined interval, being perpendicular to the impurity diffusion regions.

Abstract: A semiconductor wafer cleaning apparatus comprises an outer tank, a cleaning tank provided within the outer tank, a wafer carrier provided within the cleaning tank, a plurality of jet nozzles directed toward the wafer carrier, a main pipe connected to the jet nozzles, a circulating pump connected to the main pipe and the outer tank for circulating a cleansing solution from the outer tank, through the main pipe, the jet nozzles, and the cleaning tank, and a filter for filtering the circulated cleansing solution.

Abstract: A CCD and method of fabricating the same, which reads signal charges completely and increases the fill factor of its pixel, to improve the sensitivity. The CCD having photodiodes in matrix form, includes a first interlevel insulating layer and first transfer gate sequentially formed between the photodiodes arranged in the row direction, a block insulating layer formed along the center of the first transfer gate, a second interlevel insulating layer formed on the first transfer gate, second and third transfer gates formed on the first transfer gate, being isolated from each other on the block insulating layer, a third interlevel insulating layer formed on the second and third transfer gates, and a fourth transfer gate formed on the third interlevel insulating layer, being placed on the second and third transfer gates.

Abstract: Mask ROM cell and method of fabricating the same, is disclosed, including a semiconductor substrate of a first conductivity type, a plurality of impurity diffusion regions of a second conductivity type, formed in the semiconductor substrate in one direction, having a predetermined distance therebetween, an insulating layer formed on a portion of the semiconductor substrate, corresponding to each impurity diffusion region, a gate insulating layer formed on only a portion of the semiconductor substrate, between the impurity diffusion regions and a plurality of conductive lines formed on the gate insulating layer and insulating layer in a predetermined interval, being perpendicular to the impurity diffusion regions.

Abstract: A memory device and method of forming the same, includes a plurality of wordlines for applying a cell driving signal, a plurality of bitlines for inputting or outputting data, and a plurality of cells, each cell having a first gate, source and drain electrodes and a second gate, wherein either the first or second gate is connected to one of the wordlines, the source electrode is connected to one of the bitlines, and the drain electrode is connected to either the first or second gate which is not connected to the one wordline.

Abstract: A semiconductor wafer cleaning apparatus comprises an outer tank, a cleaning tank provided within the outer tank, a wafer carrier provided within the cleaning tank, a plurality of jet nozzles directed toward the wafer carrier, a main pipe connected to the jet nozzles, a circulating pump connected to the main pipe and the outer tank for circulating a cleansing solution from the outer tank, through the main pipe, the jet nozzles, and the cleaning tank, and a filter for filtering the circulated cleansing solution.

Abstract: The present invention relates to a diffusion barrier layer for a semiconductor device and fabrication method thereof. The diffusion barrier layer according to the present invention is fabricated by forming a diffusion barrier layer containing a refractory metal material and an insulating material on an insulating layer and in a contact hole, wherein the insulating layer being partially etched to form the contact hole, is formed on a semiconductor substrate; and annealing the diffusion barrier layer. Therefore, an object of the present invention is to provide a diffusion barrier layer for a semiconductor device, which is of an amorphous or microcrystalline state and thermodynamically stable even at a high temperature since an insulating material is bonded to a refractory metal material in the diffusion barrier layer.

Abstract: A method of forming metal thin film of a memory device includes the steps of forming a metal layer on a semiconductor substrate, forming uniform grains on a surface of the metal layer, and forming a dielectric layer on the metal layer.

Abstract: A solid-state image sensor in which an interface area between a vertical charge coupled device (VCCD) and a horizontal charge coupled device (HCCD) is formed under the HCCD, thereby maximizing charge-transferring efficiency is disclosed, including a substrate; a well formed in the substrate; a first impurity region formed in the well under the VCCD and the HCCD; and second impurity regions selectively formed in the first impurity region to have a border from the first impurity region under the HCCD, wherein the second impurity regions have a different ion concentration from the first impurity region.