Abstract: A device and method for driving a liquid crystal display (LCD). The device includes a mixer for temporarily storing digital picture signals of a plurality of channels and outputting the digital picture signals according to a predetermined order of polarity based on polarity control data, a latch unit for latching the digital picture signals output from the mixer based on predetermined pulse signals, a digital-to-analog (D/A) conversion unit for converting the digital picture signals output from the latch unit based on predetermined reference voltage signals, a storage unit for adding a predetermined value to the output signal of the D/A conversion unit when processing positive polarity signals, and a switching unit generating first and second polarity signals in a predetermined order based on the output signals of the storage unit.

Abstract: A metal wiring stricture includes a conduction line, an insulator film for electrically insulating the conduction line, and a transmutation layer formed as the density of a portion of the insulator film adjacent to the conduction line is increased or by adding impurities to the insulator film. A metal wiring forming method for a semiconductor device, includes the step of forming a trench in a given portion of a silicon oxidation film formed on a semiconductor substrate, forming a transmutation layer on a surface of the silicon oxidation film, and depositing a conductive material on the transmutation layer to form a conduction line, whereby diffusion of the conductive material is prevented.

Abstract: The present invention relates to a HCCD of a CCD image sensor comprising a channel stop region, a BCCD channel formed on the channel stop region, a plurality of first poly gates and a plurality of second poly gates formed on the BCCD channel and alternately arranged in a partially overlapping manner, and a dummy gate formed on the BCCD channel between first and second selected ones of the second poly gates.

Abstract: A Time Dependent Dielectric Breakdown (TDDB) test pattern circuit, which can reduce testing time and statistically improve a precision of measurement as well as a method for testing the test pattern circuit are discussed. Typically, a test pattern circuit includes in plurality of unit test patterns. Each unit test pattern includes a capacitor connected to a stress voltage. The stress voltage is applied to the capacitor and the current flowing from the capacitor is measured over time. The dielectric in the capacitor breaks down over time and at a certain point, the current from the capacitor changes suddenly. Unfortunately, the convention test pattern circuit requires serial testing of each unit cell, and therefore, the measuring time is significant when there are many unit cells involved. The circuit allows for the measurements to take place simultaneously for all unit cells within the test pattern circuit.

Abstract: In a semiconductor device and method for manufacturing the same, a buried insulating layer is formed on a semiconductor substrate, multiple depletion regions of a first conductivity type are formed on the buried insulating layer and separated from one another, a field oxide layer is formed among the depletion regions of the buried insulating layer, a gate oxide layer is formed on the depletion regions, a gate is formed on the gate oxide layer, impurity regions that are heavily doped with impurities of a second conductivity type is formed in the depletion regions on both sides of the gate to define a source and drain, and a counter doping layer that is lightly doped with impurities of the second conductivity type is formed under the channel defined by a portion of the depletion regions positioned between the impurity regions.

Abstract: A solid-state image sensor and a fabricating method thereof in which poly gates in a horizontal charge coupled device (hereinafter referred to as HCCD) are made to have different lengths to omit a barrier ion implanting process step, thus simplifying the entire process and maximizing the charge-transferring efficiency are disclosed, the solid-state image sensor having an HCCD and VCCDs including a well region of a second conductivity type formed in a semiconductor substrate of a first conductivity type; a HCCD of the first conductivity type formed on the well region of the second conductivity type; and a plurality of polygate electrodes having sequentially different lengths repeatedly formed on the semiconductor substrate.

Abstract: Disclosed are a method for forming a structure of wires for a semiconductor device in which pads are formed for contact in cell regions as well as core regions and periphery regions where cell aspect ratios are very high, and a structure of wires so formed. The semiconductor device includes a semiconductor substrate arranged into cell regions and periphery and/or core regions, the periphery and/or core regions having a well formed in the semiconductor substrate, the semiconductor substrate being arranged into active regions and field regions, the semiconductor device also having field insulating layers in the field regions, plural gate structures on portions of the semiconductor substrate in the active regions, and impurity regions in the semiconductor substrate between the gate structures.

Abstract: An instruction decoding unit in a microcomputer is disclosed having an instruction word capable of being selected by a user to conveniently produce application software while maintaining security. The decoding unit in a microcomputer includes an instruction register for storing instructions fetched from a memory, an instruction decoder for decoding instruction codes of the instructions stored in the instruction register and for designating micro-instructions to be executed, a micro-ROM for outputting a series of the micro-instructions designated by the instruction decoder, and a user instruction selector for selecting or changing the micro-instructions of the micro-ROM in response to user's selection so as to change the operation of an instruction word.

Abstract: TDDB test pattern which can reduce a test time period and improve a precision of a measurement result statistically; and a method for testing TDDBs of MOS capacitor dielectric films using the same, the TDDB test pattern including a plurality of unit test pattern cells each having an MOS capacitor, an MOS transistor, and a fuse for controlling operations of the MOS capacitor and the MOS transistor, a first voltage supplying unit for supplying a stress voltage to the MOS capacitor and the MOS transistor in each unit test pattern cell on the same time, an ammeter for continuous measurement of a total current from the plurality of unit test pattern cells, to measure a total time to breakdown of the plurality of unit test pattern cells, a plurality of VFN's (Voltage Forcing Nodes) each positioned between the first voltage supplying unit and the fuse in the unit test pattern cell, a DCMN (Drain Current Measuring Node) positioned between the ammeter and a drain terminal of the MOS transistor in each of the plur

Abstract: A DRAM cell capacitor having a high capacitance is obtained by forming a lower capacitor electrode of TiN and a roughened tungsten film on the TiN layer. A high dielectric constant film, such as tantalum pentaoxide, is then provided on the tungsten film and an upper capacitor electrode is deposited on the dielectric film. A method of forming the roughened tungsten film includes the step of depositing tungsten on the TiN layer at a temperature in the range of 200-650° C.

Abstract: A SOI device in which floating body effect is reduced to improve performance. The SOI device including a semiconductor substrate; a first buried insulating film formed on the semiconductor substrate; a first conductivity type silicon layer formed on the first buried insulating film; an active region and a first conductivity type semiconductor layer formed to be isolated on predetermined areas of the first conductivity type silicon layer; second buried insulating films formed to be isolated from one another in the first conductivity type silicon layer to connect the first conductivity type semiconductor layer with the active region through the first conductivity type silicon layer; a gate electrode formed on the active region; impurity region formed in the semiconductor substrate at both sides of the gate electrode; and contact pads formed on the first conductivity type silicon layer.

Abstract: A capacitor includes a substrate, an insulating layer on the substrate, the insulating layer having a contact hole, a first storage node in the contact hole and on the insulating layer, a second storage node on a peripheral portion of the first storage node, the second storage node having a planar top surface, a dielectric layer on the surface of the first and second storage nodes, and a plate node on the dielectric layer.

Abstract: A data transmission device which improves data transmission efficiency is disclosed. A data transmission device includes a decoder converting a first binary data to a ternary data, a ternary data generator coupled to the decoder and generating three logic levels corresponding to a power source voltage, an intermediate voltage, and a ground voltage, the intermediate voltage having a voltage level between the power source voltage and the ground voltage, a ternary data detector coupled to the ternary data generator and converting the three logic levels from the ternary data generator to pairs of second binary data, and an encoder coupled to the data detector and restoring the pairs of second binary data to the first binary data.

Abstract: A contactless, nonvolatile metal oxide semiconductor memory device having a rectangular array of memory cells interconnected by word-lines in the row direction of the array and bit-lines in the column direction of the array. Each memory cell has a structurally asymmetrical pair of floating gate, MOS field effect transistors of the same row that share a common source region (bit line) within a semiconductor substrate. The asymmetry of the structure of the floating gates of the two transistors enables programming/reading and monitoring of the cell to be effected simultaneously. The structure of the floating gate is also responsible for a relatively large capacitive coupling between the floating gates and the control gate (word line) which lies above them. Since the floating gates essentially serve as a mask for implantation of program/read and monitor drain regions within the substrate, fabrication of the device incorporates self-aligning process steps.

Abstract: A method of fabricating a nonvolatile memory device having a first conductivity type substrate, includes the steps of forming a gate insulating layer on the entire surface of the semiconductor substrate, forming a plurality of floating gate lines on the gate insulating layer, forming first sidewall spacers on both sides of each floating gate, forming a plurality of impurity regions having a second conductivity type in the substrate between the floating gate lines, forming a dielectric layer on the floating gate lines, forming a plurality of control gate lines on the dielectric layer, forming second sidewall spacers on both sides of the control gate lines, selectively etching the dielectric layer and the floating gate lines to form a plurality of floating gates, forming tunneling insulating layers on both sides of the floating gates, and forming a plurality of program lines between the impurity regions.

Abstract: Provided with a contact hole of a semiconductor device and its forming method which is adapted to form double slopes in the insulating layer, with the contact hole including an insulating layer formed on a semiconductor substrate, and a contact hole having double slopes, exposing a defined region of the semiconductor substrate.

Abstract: A method for fabricating a capacitor in a DRAM cell, includes the steps of: forming a plurality of wordlines each having a first cap insulating film on a semiconductor substrate; forming source/drain impurity regions in an active region of the semiconductor substrate on both sides of each of the wordlines; forming first sidewall insulating films at the both sides of said each of the wordlines; forming first plugs for contacting either capacitor nodes or bitlines on each of the source/drain impurity regions; forming an interlayer insulating film on the semiconductor substrate and forming a contact hole to the first plugs for contacting to the bitlines therein; forming a plurality of bitlines in a direction perpendicular to the wordlines, each of the bitlines being in contact with the first plugs, and having a second cap insulating film; forming second sidewall insulating films at both sides of each of the bitlines and selectively removing the interlayer insulating film to expose surfaces of the first plugs; fo

Abstract: BLP stack is disclosed which has a higher reliability and a less area of mounting for providing a denser package, including a first package having external power connection leads each started to be exposed through a bottom thereof and extended to a top surface through a side surface inclusive of bottom lead portions on a bottom surface, side lead portions on a side surface, and upper lead portions on a top surface, and a second package having external power connection leads started to be exposed through a bottom thereof and brought into contact with the external power connection leads on the first package to be electrically connected thereto.

Abstract: Solid state image sensor having photodiode regions for converting optical image signal into an electrical signal and charge coupled device regions for transferring video charges generated in the photodiode regions in one direction, including first microlens layers spaced from one another and formed over the photodiode regions to be opposite thereto for focusing lights onto the photodiode regions, and second microlens layers formed of a material having a refractive index greater than the first microlens layers on an entire surface of the first microlens layers for focusing lights incident to edge portions of the first microlens layers and spaces between the first microlens layers onto the photodiode regions.

Abstract: An SRAM cell and method for fabricating the same including first and second access transistors, first and second drive transistors, and first and second load resistors. A first terminal of the first access transistor, a gate terminal of the second drive transistor, and a first load resistor terminal are connected to one another to form a first cell node terminal. A first terminal of the second access transistor, a gate terminal of the first drive transistor, and a second load resistor terminal are connected to one another to form a second cell node terminal. The SRAM cell includes a gate electrode of each of the first and second drive transistors arranged over a semiconductor substrate in a first direction, and a gate electrode of each of the first and second access transistors arranged in the first direction overlapped with portions of the gate electrodes of the first and second drive transistors.