Abstract: Circuits and methods that improve the performance of electronic sampling systems are provided. Impedances associated with sampling semiconductor switches are maintained substantially constant during sample states, at least in part, by compensating for encountered input signal variations in order to reduce or minimize signal distortion associated with sampled signals that pass through the sampling switch.

Abstract: A technique for cancelling out target IM2 components in a wireless receiver's mixer output is disclosed. A differential RF signal and a differential local oscillator (LO) signal are mixed by a mixer to demodulate the RF signal. A first common node signal is generated between a first resistor and a second resistor coupled across the mixer's differential output terminals. A second common node signal is generated between a third resistor and a fourth resistor coupled across the differential output terminals, where a capacitor is coupled between the second common node and a power supply terminal. The second common node signal provides a stable reference signal for IM2 components above a certain frequency. The two common node signals are subtracted to create a difference signal. The difference signal is scaled by a scaling factor obtained during calibration. The scaled difference signal is coupled to the mixer output to offset IM2 distortion.

Abstract: A low side clamp circuit has a control portion, a sense portion, and a clamp portion. When the sense portion detects that the input voltage of an output stage of a buffer has gone below a threshold voltage, it triggers the control portion to quickly turn on a clamp transistor (in the clamp portion) to clamp the output voltage to the clamp voltage. The control portion and sense portion have cross-coupled transistors that create increased speed and a sharp response with little or no voltage offset with a wide range of load currents. A clamp current source draws current through a resistor coupled in series between the base of the output transistor in the control portion and the collector of the output transistor in the sense portion. The clamp current is set to ClLo/R, where ClLo is the clamp voltage. A high side clamp is also described.

Abstract: A current sensor is disclosed. The current sensor includes a leadframe having a die paddle, a portion of the die paddle being configured as a resistive element through which current can flow, and an integrated circuit (IC) die attached and thermally coupled to the die paddle. The IC die includes a current sensing module configured to measure a voltage drop across the resistive element and convert the voltage drop measurement to a current measurement signal and a temperature compensation module electrically coupled to the current sensing module. The temperature compensation module is configured to adjust the current measurement signal to compensate for temperature-dependent changes in the resistive element. The temperature compensation module includes a temperature-sensitive element, with a portion of the temperature-sensitive element located directly over a portion of the resistive element.

Abstract: An anemometer and method for analyzing fluid flow is described. In one embodiment, a transistor sensor is heated by applying power to cause its base-emitter junction to rise from an ambient first temperature to a second temperature. The power is removed, and the Vbe is measured at intervals as the junction cools. The Vbe equates to a temperature of the junction. The temperature exponentially decreases, and the time constant of the decay corresponds to the fluid flow velocity. A best fit curve analysis is performed on the temperature decay curve, and the time constant of the exponential decay is derived by a data processor. A transfer function correlates the time constant to the fluid flow velocity. The transistor is thermally coupled to a metal rod heat sink extending from the package, and the characteristics of the rod are controlled to adjust the performance of the anemometer.

Abstract: Circuits and methods for converting a signal from analog to digital. A random number generator provides a random number to a memory. The memory is preconfigured to include codes of predetermined digital to analog (DAC) configurations that provide the maximum amount of DAC gradient suppression. At least one Flash reference generation DAC (FRGD) has an input coupled to the memory unit and an output providing a reference voltage level for its respective Flash comparator. The Flash comparators compare the analog input signal to their respective reference voltage and provide a digital output signal based on the comparison.

Abstract: Technique for providing power to a powered device (PD) over a cable having first and second sets of twisted pairs, such as signal pairs and spare pairs. Power Sourcing Equipment (PSE) circuitry is coupled via a first switch to the second set, e.g. to the spare pairs. A switch control circuit turns the first switch off to enable the PSE circuitry to perform a prescribed operation in connection with the PD over only the first set, e.g. over the signal pairs, and turns the first switch on to enable the PSE circuitry to perform the prescribed operation in connection with the PD over the first and second sets.

Abstract: Three modifications are provided to obtain a fast and accurate average current limit in a DC/DC converter. The first modification relates to providing a bias signal control configured to apply a variable DC bias signal to the compensation ramp signal generated in the DC/DC converter so that the compensating ramp signal is biased to zero at the end of each ON-time for each cycle so that the peak current limit is independent of the duty cycle of the pulse width modulation signal during current limit conditions. A second modification relates to modulating the clamp voltage that establishes the peak current limit as a function of ripple of the inductor current for each cycle of the pulse width modulation signal so as to reduce or cancel the effect of the inductor ripple current on the average output current during current limit conditions.

Abstract: An apparatus and method for a portable device incorporating a battery and a battery charger. In the portable device, there are a plurality of system components configured to facilitate a plurality of functions that the portable device is designed to perform. The battery in the portable device is configured for providing an internal power supply to the plurality of system components in the absence of an external input power supply. The battery charger is configured for charging the battery when the external input power supply is available. The battery charger disclosed herein is capable of supplying system power to the system components when voltage of the battery that is being charged is below a limit, thereby allowing the portable device to operate when voltage of the battery drops below the limit.

Abstract: A temperature compensation circuit for generating a temperature compensating reference voltage (VREF) may include a Bandgap reference circuit configured to generate a Bandgap reference voltage (VBGR) that is substantially temperature independent and a proportional-to-absolute-temperature reference voltage (VPTAT) that varies substantially in proportion to absolute temperature. The circuit may also include an operational amplifier that is connected to the Bandgap reference circuit and that has an output on which VREF is based. The circuit may also include a feedback circuit that is connected to the operational amplifier and to the Bandgap reference circuit and that is configured so as to cause VREF to be substantially equal to VPTAT times a constant k1, minus VBGR times a constant k2.

Abstract: An analog-to-digital converter system and methodology comprising an analog-to-digital converter circuit configured to provide sequentially a plurality of codes designating a numerical value in a first number system. The analog-to-digital converter system further comprising an encoder interface circuit configured to receive the plurality of codes and to derive a redundant digital representation. A portion of the redundant digital representation is transmitted during the conversion period. The encoder interface circuit may be configured to use a numerical successive-approximation algorithm to derive the redundant digital representation. A substantial portion of the redundant digital representation may be transmitted via a serial interface during the conversion period to reduce an overall latency.

Abstract: A technique for combining power to a single load from multiple power supplies using power over Ethernet (PoE) is disclosed. Each power supply is coupled to associated power sourcing equipment (PSE) providing PoE, and each PSE has a current limit. The power supplies supply approximately the same voltage, but the output voltages are typically not exactly equal. All the power supplies are connected via diodes to a common load terminal. The power supply outputting the highest voltage first supplies power to the load terminal, since only its diode is forward biased, until a PoE current limit is reached. Then its duty cycle is limited. The load terminal voltage is then inherently lowered to cause the diode of the power supply with the next highest output voltage to connect it to the load to supply additional power to the load as the first power supply continues to supply its limited current.

Abstract: A current mode power conversion system and method operates in cycles. Each cycle includes an on time and an off time. The system includes an inductor connected to store energy during the on time of each cycle and use the energy during the off time of each cycle. The system provides a stable output voltage and a maximum-limited output current to a load during constant load conditions. The system comprises a feedback control linearly operable so as to control the output voltage across the load during constant load conditions, and non-linearly operable so as to control the output voltage across the load during certain detected changes in load conditions as a function of the derivative of the current in the inductor so as to speed up the transient response of the power conversion system when a fault condition exists.

Abstract: Novel system and methodology are provided for controlling a DC/DC forward converter having a transformer with primary and secondary windings, a reset switch, and a first switch coupled to the primary winding of the transformer. The control system involves a PWM control circuit responsive to an output signal of the converter for producing a PWM signal to control switching of the reset switch, and the first switch. A period of the PWM signal includes an on-time interval for enabling transfer of power via the transformer when the first switch is on, and a reset time interval for enabling reset of the transformer when the reset switch is on. A maximum value of the on-time interval is pre-set to provide sufficient time for the reset. The reset switch is turned off when the PWM signal goes from a first level to a second level. A first delay period is set between time when the reset switch turns off and time when the first switch turns on.

Abstract: A common mode bias circuit may include a weak common mode bias generator and a common mode bias capacitance. During a first state of the common mode bias circuit, the weak common mode bias generator may be coupled to the common mode bias capacitance and may impart to them a predefined common mode signal level. During a second state of the common mode bias circuit, the common mode bias capacitance may be coupled to differential inputs of an amplifier in a manner that establishes an input common mode level for the amplifier.

Abstract: Circuits and methods for paralleling voltage regulators are provided. Improved current sharing and regulation characteristics are obtained by coupling control terminals of the voltage regulators together which results in precise output voltages and proportional current production. Distributing current generation among multiple paralleled voltage regulators improves heat dissipation and thereby reduces the likelihood that the current produced by the voltage regulators will be temperature limited.

Abstract: A mixer in an RF demodulator includes a transconductance amplifier that converts an RF input voltage (Vin), applied to the base of a first bipolar transistor, to a first output current. The first output current contains third order intermodulation (IM3) products. An IM3 canceller is connected in parallel with the transconductance amplifier. The base of a second bipolar transistor in the IM3 canceller is coupled to the DC component of Vin, and the AC component of Vin is coupled to the emitter of the second bipolar transistor, such that the currents though the first bipolar transistor and the currents through the second bipolar transistor change oppositely. The collectors of the transistors are coupled together. The values of components in the IM3 canceller are set so that the current generated by the IM3 canceller substantially cancels IM3 distortion in the first current or other current generated in a demodulator of Vin.

Abstract: This disclosure describes a circuit implementation providing the functions necessary to implement an isolated I2C bidirectional port. The technique implements a current source as a pull up device on at least one side of the isolation system. The circuit manages and communicates bidirectional data across an isolation barrier. A method of communicating bidirectional signals and an I2C acknowledge (ACK) or clock stretching through an isolation channel is disclosed.

Abstract: A buck-boost converter with a switch controller may cause switches A, B, C, and/or D to cyclically close such that switches B and C are closed during at least one interval of each cycle during both the buck and boost modes of operation. The switch controller may in addition or instead cause switches A, B, C, and/or D to cyclically close based on a control signal such that switches A and D are closed during an interval of each cycle and such that these intervals are never both simultaneously modulated by a small change in the control signal during any mode of operation.

Abstract: In a current mode controlled switching power supply, current through the inductor is sensed to determine when to turn off or on the switching transistors. The inductor current has a higher frequency AC component and a lower frequency DC component. The AC current feedback path, sensing the ramping ripple current, is separate from the DC current path, sensing the lower frequency average current. Separating the current sensing paths allows the signal to noise ratio of the AC sense signal to be increased and allows the switching noise to be filtered from the DC sense signal. The gain of the DC sense signal is adjusted so that the DC sense signal has the proper proportion to the AC sense signal. The AC sense signal and the DC sense signal are combined by a summing circuit. The composite sense signal is applied to a PWM comparator to control the duty cycle of the switch.