Abstract: Driver circuitry with a tuned output impedance is provided. Tuning is provided by an isolation circuit and matching network coupled to an output of the driver circuit. The isolation circuit isolates the capacitance associated portions of the driver circuit thereby reducing overall output capacitance. The matching network substantially compensates for reactive impedances associated with other portions of the driver circuit. These tuning circuits allow the driver circuit overcome intrinsic reactance and exhibit a substantially resistive output impedance characteristic.

Abstract: A CMOS switch with compensation circuitry that maintains linearized gate capacitance, said switch capable of selectively processing a signal independent of changes to gate capacitance current. The switch passes signals which are substantially insensitive to changes in source impedance. Thus, the switch processes an analog signal with a minimum of distortion as a result of gate capacitance currents.

Abstract: A slope compensation circuit that provides slope compensation signals for switching voltage regulators is provided. The slope compensation circuit includes a feedback circuit, a control circuit, and a slope signal generator circuit. The feedback circuit generates a feedback signal that is indicative of both input and output voltages. The control circuit acts as a voltage controlled resistor that varies its resistance based on the feedback signal in order to control the slope signal generator circuit so that an optimum amount of slope compensation is provided.

Abstract: The present invention provides a capacitor charging circuit that efficiently charges capacitive loads. In particular, circuits and techniques are preferably provided for using current from both the primary and secondary windings of a transformer to control ON-time and OFF-time of a switch. This arrangement preferably yields an adaptable ON-time and adaptable OFF-time switch that is capable of rapidly charging capacitor loads ranging from as low as zero volts to several hundred volts. The output voltage is preferably measured indirectly to prevent unnecessary power consumption. In addition, control circuitry can be provided to conserve power by ceasing the delivery of power to the capacitor load once the desired output voltage is reached. Control circuitry preferably operates an interrogation timer that periodically activates the power delivery cycle to maintain the capacitor output load in a constant state of readiness.

Abstract: A current-mode switching regulator that maintains a substantially constant maximum current limit over a virtually full range of duty cycles is provided. The regulator has a control circuit that includes a buffer circuit, an adjustable voltage clamp circuit, and a slope compensation circuit. The buffer circuit isolates a control signal from capacitive loading associated with control circuit. The threshold level of the adjustable voltage clamp circuit varies with respect to the amount of slope compensation provided to the voltage regulator. This allows a control voltage to increase as slope compensation increases so that a substantially constant maximum current limit is maintained.

Abstract: A circuit that provides the root-mean-square (RMS) value of an input signal and that detects and independently recovers from an output fault condition is provided. The circuit includes reconfigurable circuitry that changes from normal operating mode to fault recovery mode when an output fault is detected. During fault recovery mode, the circuit provides a modified output signal that allows independent recovery from an output fault condition. Once recovery is complete, the circuit returns to normal operating mode and provides a DC output signal proportional to the RMS value of an AC input signal.

Abstract: The present invention provide systems and methods for reducing a reverse recovery current through a body diode in a synchronous switching transistor. An inductor is coupled in the commutation path of the body diode of the synchronous switching transistor. The inductor slows the rate of increase of the reverse recovery current to reduce avalanche effects in the synchronous switching transistor. This reduces the peak reverse recovery current through the body diode of the synchronous switching transistor when the body diode commutates, thereby reducing power dissipation in the main switching transistor. An inductor may be coupled to both switching transistors so that power dissipation is reduced if the regulator is operated as a buck or boost regulator. A diode and a reverse recovery switcher may be coupled to the inductor to transfer energy in the inductor back to the input or output capacitor after the body diode commutates.

Abstract: Adaptive filters are presented that dynamically adjust the level of filtering of signals output from a sigma-delta or noise-shaping pulse code modulator RMS-to-DC converter to efficiently remove noise to improve accuracy without unduly increasing conversion response time. The level of filtering is adjusted in accordance with criteria responsive to either input signal changes (e.g., variance), input signal frequency, or both. Filtering can be analog or digital.

Abstract: A current-mode switching regulator that maintains a substantially constant maximum current limit over a virtually full range of duty cycles is provided. The regulator has a control circuit that includes a buffer circuit, an adjustable voltage clamp circuit, and a slope compensation circuit. The buffer circuit isolates a control signal from capacitive loading associated with control circuit. The threshold level of the adjustable voltage clamp circuit varies with respect to the amount of slope compensation provided to the voltage regulator. This allows a control voltage to increase as slope compensation increases so that a substantially constant maximum current limit is maintained.

Abstract: Recovery systems and methods of the present invention include circuitry that transfers energy from an input to an output with reduced power dissipation. A synchronous switching regulator is one application for the recovery system of the present invention. An inductor may be used in a synchronous switching regulator to reduce power dissipation caused by reverse recovery current that flows through the body diode of the synchronous switching transistor when the synchronous switching transistor turns OFF. Energy in the inductor may be transferred back to the input or output capacitor of the switching regulator through a recovery system of the present invention. The recovery circuit of the present invention provides an efficient method for intercepting energy in the inductor, and presenting power to a recovery switcher in a manner that allows the recovery switcher to transfer the energy into the input or output capacitor of the switching regulator efficiently.

Abstract: A high voltage MOS transistor with a gate extension that has a reduced electric field in the drain region near the gate is provided. The high voltage MOS transistor includes a first and second gate layers, and a dielectric layer between the gate layers. The first and second gate layers are electrically coupled together and form the gate of the transistor. The second gate layer extends over the drain of the transistor above the dielectric and gate oxide layers to form the gate extension. The high voltage MOS transistor of the present invention may be fabricated without additional processing steps in BiCMOS and CMOS processes that use dual polysilicon layers and a dielectric layer that are used to form capacitors.

Abstract: A signal processor circuit that buffers a ground-referred, signal-dependent, current. A ground-referred node in the circuit is preferably maintained at a ground level. The ground-referred, signal-dependent, current is preferably buffered such that the ground-referred node is preferably maintained at a ground level independent of changes to the ground-referred, signal-dependent, current.

Abstract: Methods for synchronizing non-constant frequency switching regulators with a phase locked loop are disclosed. The methods enable non-constant frequency switching regulators to be synchronized with a phase locked loop to achieve constant frequency operation in steady state while retaining the advantages of non-frequency operation to improve transient response and operate over a wider range of duty cycles. In addition, the methods enable multiple non-constant frequency regulators to be synchronized and operated in parallel to deliver higher power levels to the output than a single switching regulator.

Abstract: Power measuring receiver (PMR) methods and apparatus for measuring power of signals are provided in which a high frequency measuring circuit (HFMC), a conversion measuring circuit (CMC), and an intermediate frequency measuring circuit (IFMC) work in conjunction with each other to measure a wide power range of signals. The HFMC may measure relatively high power signals at high frequency. The CMC may convert the high frequency signal into an intermediate frequency signal so that both the CMC and the IFMC can accurately measure low power signals. The CMC may also set the minimum noise bandwidth associated with gain stages in the IFMC. The intermediate frequency may provide the IFMC with the ability to perform low power measurements at a reduced DC power consumption.

Abstract: Circuits and methods for controlling load sharing by multiple power supplies are provided. In preferred embodiments, load share controllers utilize multiple voltage control loops to monitor the output voltages that are being provided by multiple power supplies connected to a load. These voltage control loops each generate a voltage control voltage that is proportional to the difference between the actual output voltage of the corresponding power supply and the desired output voltage. The voltage control loop with the highest voltage control voltage then controls a current control voltage generated in a current control loop for each power supply via a share bus. These current control loops then regulate the current provided by the corresponding power supplies so that those currents are all proportional to the voltage on the share bus.

Abstract: Methods for synchronizing non-constant frequency switching regulators with a phase locked loop are disclosed. The methods enable non-constant frequency switching regulators to be synchronized with a phase locked loop to achieve constant frequency operation in steady state while retaining the advantages of non-frequency operation to improve transient response and operate over a wider range of duty cycles. In addition, the methods enable multiple non-constant frequency regulators to be synchronized and operated in parallel to deliver higher power levels to the output than a single switching regulator.

Abstract: Methods and circuits implementing a constant-current/constant-voltage circuit architecture are provided. The methods and circuits preferably provide a charging system that provides current to a load using a fixed current until the load is charged. When the load is charged, the methods and circuits preferably provide a variable current to the load in order to maintain the voltage level across the load. This variable current varies according to the voltage across the load. In one embodiment of the invention, a constant power current may also be used as one of the load charging currents. The constant power current may act as a limit on the charging circuit's power output.

Abstract: Circuits and methods for controlling load sharing by multiple power supplies are provided. In preferred embodiments, load share controllers utilize multiple voltage control loops to monitor the output voltages that are being provided by multiple power supplies connected to a load. These voltage control loops each generate a voltage control voltage that is proportional to the difference between the actual output voltage of the corresponding power supply and the desired output voltage. The voltage control loop with the highest voltage control voltage then controls a current control voltage generated in a current control loop for each power supply via a share bus. These current control loops then regulate the current provided by the corresponding power supplies so that those currents are all proportional to the voltage on the share bus.

Abstract: Methods for synchronizing non-constant frequency switching regulators with a phase locked loop are disclosed. The methods enable non-constant frequency switching regulators to be synchronized with a phase locked loop to achieve constant frequency operation in steady state while retaining the advantages of non-frequency operation to improve transient response and operate over a wider range of duty cycles. In addition, the methods enable multiple non-constant frequency regulators to be synchronized and operated in parallel to deliver higher power levels to the output than a single switching regulator.

Abstract: A multi-phase multi-channel voltage regulator having high efficiency at light loads is provided. The regulator increases efficiency at light loads by shutting down a select channel of the regulator. In addition, the regulator may place remaining channels in Burst Mode.