Patents Assigned to Linear Technology
  • Methods and circuits for more accurately mirroring current over a wide range of input current
    Patent number: 6897717
    Abstract: The present invention comprises methods and circuits for mirroring input current in multiple stages to improve the accuracy of the mirrored output current over a wide dynamic range of input current. The current mirror circuit of the present invention automatically (1) detects an increasing magnitude of input current and (2) adapts the current mirror circuit to accommodate the increasing magnitude.
    Type: Grant
    Filed: January 20, 2004
    Date of Patent: May 24, 2005
    Assignee: Linear Technology Corporation
    Inventors: Daniel Eddleman, Christopher Umminger
  • Bidirectional power conversion with multiple control loops
    Patent number: 6894461
    Abstract: Bidirectional power conversion systems provide the ability to change power attributes to and from a component. Current bidirectional power conversion systems use a unidirectional power converter for each direction. The integration of the two normally independent power converters results in a bidirectional power converter with nearly half the size, weight, volume, cost and complexity. Described are embodiments of bidirectional power conversion systems that allow power transfer between two or more components without requiring the use of separate unidirectional power converters.
    Type: Grant
    Filed: October 11, 2002
    Date of Patent: May 17, 2005
    Assignee: Linear Technology Corp.
    Inventors: Thomas P. Hack, Robert C. Dobkin
  • Low voltage high gain amplifier circuits
    Patent number: 6891433
    Abstract: In one embodiment, the present invention provides an amplifier circuit including a cascode input stage coupled to a differential stage. In another embodiment, an amplifier includes a differential stage coupled to a common gate stage. Embodiments of the present invention also include an improved low voltage amplifier using a 3-stage topology including a wide-swing folded-cascode input stage followed by a differential gain stage which provides improved gain and output compliance. Embodiments of the present invention improve the available cascode stage headroom and reject process and temperature induced parametric variations.
    Type: Grant
    Filed: July 11, 2003
    Date of Patent: May 10, 2005
    Assignee: Linear Technologies Corporation
    Inventor: Victor Paul Schrader
  • High voltage transistors with graded extension
    Patent number: 6888207
    Abstract: High voltage transistors with high breakdown voltages are provided. These high voltage transistors are formed with graded drain extension regions. The concentration of charge carriers increases farther away from the gate across each drain extension region, causing severe electric fields to be moved away from the gate. Methods and structures of the present invention may be used to increase a transistor's breakdown voltage to the theoretical limit of the device. High voltage transistors with graded extension regions may be p-channel or n-channel MOSFETs.
    Type: Grant
    Filed: October 10, 2003
    Date of Patent: May 3, 2005
    Assignee: Linear Technology Corporation
    Inventor: Francois Hebert
  • Synthetic circuit component and amplifier applications
    Patent number: 6879215
    Abstract: Synthetic circuit elements and amplifier applications for synthetic circuit elements are provided. The synthetic circuit elements disclosed herein may be configured to compensate for some or all of the parasitic capacitance normally associated with circuit elements disposed on a substrate providing a selectable impedance characteristic. Amplifier circuit constructed using such synthetic circuit elements exhibit improved performance characteristics such as improved recovery time, frequency response, and time domain response.
    Type: Grant
    Filed: May 10, 2002
    Date of Patent: April 12, 2005
    Assignee: Linear Technology Corporation
    Inventor: Steven D. Roach
  • Load-generated drive, substantially no quiescent current, techniques and circuits for high speed switching of transistors
    Patent number: 6861892
    Abstract: Techniques and circuits for high speed switching of transistors are provided. These techniques and circuits switch an output device while varying the drive current to the output device in proportion to the output current through the output device. In addition, these techniques and circuits provide a switching circuit with substantially no quiescent currents. This is accomplished by sampling the output current conducted by the output device and using the sample as a signal to drive either the output device fully ON or to switch the output device fully OFF.
    Type: Grant
    Filed: January 22, 2003
    Date of Patent: March 1, 2005
    Assignee: Linear Technology Corporation
    Inventor: Karl Edwards
  • Voltage overshoot reduction circuits
    Patent number: 6853565
    Abstract: Feedback circuits capable of preventing output voltage overshoot in closed-loop DC regulated power supplies are presented. The circuits employ hysteresis at the input of an operational amplifier to improve the response time of the feedback circuits to a rising output voltage reaching a threshold. The feedback circuits substantially reduce, if not prevent, output voltage overshoot during start-up and hard and soft output shorts.
    Type: Grant
    Filed: May 23, 2003
    Date of Patent: February 8, 2005
    Assignee: Linear Technology Corporation
    Inventor: Chiawei Liao
  • High-speed, current driven latch
    Patent number: 6847245
    Abstract: A high-speed, current-driven latch is provided. The latch conducts a current and includes an output, a SET circuit and a RESET circuit. The output is variable between a first state and a second state. The SET circuit conducts the current present in the latch at the first state such that the SET circuit is maintained close to a level required to change the output of the transistor from the first to the second level, and the RESET circuit conducts the current at the second level such that the RESET circuit is close to a level required to change the output of the transistor from the second level to the first level.
    Type: Grant
    Filed: January 22, 2003
    Date of Patent: January 25, 2005
    Assignee: Linear Technology Corp.
    Inventor: Karl Edwards
  • Low voltage high gain amplifier circuits
    Publication number: 20050007195
    Abstract: In one embodiment, the present invention provides an amplifier circuit including a cascode input stage coupled to a differential stage. In another embodiment, an amplifier includes a differential stage coupled to a common gate stage. Embodiments of the present invention also include an improved low voltage amplifier using a 3-stage topology including a wide-swing folded-cascode input stage followed by a differential gain stage which provides improved gain and output compliance. Embodiments of the present invention improve the available cascode stage headroom and reject process and temperature induced parametric variations.
    Type: Application
    Filed: July 11, 2003
    Publication date: January 13, 2005
    Applicant: Linear Technology Corporation
    Inventor: Victor Schrader
  • Circuits and methods for synchronizing non-constant frequency switching regulators with a phase locked loop
    Publication number: 20050001602
    Abstract: Methods for synchronizing non-constant frequency switching regulators with a phase locked loop are disclosed. The methods enable non-constant frequency switching regulators to be synchronized with a phase locked loop to achieve constant frequency operation in steady state while retaining the advantages of non-frequency operation to improve transient response and operate over a wider range of duty cycles. In addition, the methods enable multiple non-constant frequency regulators to be synchronized and operated in parallel to deliver higher power levels to the output than a single switching regulator.
    Type: Application
    Filed: July 2, 2004
    Publication date: January 6, 2005
    Applicant: Linear Technology Corporation
    Inventors: Christopher Umminger, Randy Flatness
  • Apparatus for power measuring receiver
    Patent number: 6836105
    Abstract: Power measuring receiver (PMR) methods and apparatus for measuring power of signals are provided in which a high frequency measuring circuit (HFMC), a conversion measuring circuit (CMC), and an intermediate frequency measuring circuit (IFMC) work in conjunction with each other to measure a wide power range of signals. The HFMC may measure relatively high power signals at high frequency. The CMC may convert the high frequency signal into an intermediate frequency signal so that both the CMC and the IFMC can accurately measure low power signals. The CMC may also set the minimum noise bandwidth associated with gain stages in the IFMC. The intermediate frequency may provide the IFMC with the ability to perform low power measurements at a reduced DC power consumption.
    Type: Grant
    Filed: February 15, 2003
    Date of Patent: December 28, 2004
    Assignee: Linear Technology Corporation
    Inventor: Min Z. Zou
  • High voltage MOS transistor with gate extension
    Publication number: 20040227204
    Abstract: A high voltage MOS transistor with a gate extension that has a reduced electric field in the drain region near the gate is provided. The high voltage MOS transistor includes a first and second gate layers, and a dielectric layer between the gate layers. The first and second gate layers are electrically coupled togther and form the gate of the transistor. The second gate layer extends over the drain of the transistor above the dielectric and gate oxide layers to form the gate extension. The gate extension reduces the peak electric field in the drain by providing a wide area for the voltage to drop between the drain and the gate of the transistor. The dielectric layer also reduces the peak electric field in the drain near the gate by providing insulation between the gate and the drain. A lower electric field in the drain reduces the impact generation rate of carriers.
    Type: Application
    Filed: June 28, 2004
    Publication date: November 18, 2004
    Applicant: Linear Technology Corporation
    Inventor: Francois Hebert
  • Constant-current/constant-voltage circuit architecture
    Patent number: 6819094
    Abstract: Methods and circuits implementing a constant-current/constant-voltage circuit architecture are provided. The methods and circuits preferably provide a charging system that provides current to a load using a fixed current until the load is charged. When the load is charged, the methods and circuits preferably provide a variable current to the load in order to maintain the voltage level across the load. This variable current varies according to the voltage across the load. In one embodiment of the invention, a constant power current may also be used as one of the load charging currents. The constant power current may act as a limit on the charging circuit's power output.
    Type: Grant
    Filed: November 17, 2003
    Date of Patent: November 16, 2004
    Assignee: Linear Technology Corporation
    Inventors: Trevor W. Barcelo, Robert L. Reay, David M. Dwelley
  • High voltage MOS transistor with up-retro well
    Publication number: 20040224472
    Abstract: A high voltage MOS transistor is provided that is compatible with low-voltage, sub-micron CMOS and BiCMOS processes. The high voltage transistor of the present invention has dopants that are implanted into the substrate prior to formation of the epitaxial layer. The implanted dopants diffuse into the epitaxial layer from the substrate during the formation of the epitaxial layer and subsequent heating steps. The implanted dopants increase the doping concentration in a lower portion of the epitaxial layer. The implanted dopants may diffuse father into the epitaxial layer than dopants in the buried layer forming an up-retro well that prevents vertical punch-through at high operating voltages for thin epitaxial layers. In addition, the doping concentration below the gate may be light so that the threshold voltage of the transistor is low.
    Type: Application
    Filed: June 1, 2004
    Publication date: November 11, 2004
    Applicant: Linear Technology Corporation
    Inventor: Francois Hebert
  • Systems and methods for conserving energy in a switching circuit
    Patent number: 6809503
    Abstract: A switch recovery circuit is disclosed for improving the efficiency of switching voltage regulators. The switch recovery circuit includes a first and second inductor, a capacitor, a first diode, and a recovery circuit. The capacitor and diode comprise an AC coupled loop circuit around the first inductor. Current flows through the loop circuit soon after the switch is opened and charges the capacitor. The recovery circuit, which includes a second inductor that is magnetically coupled to the first inductor, provides current, at least some of which discharges the capacitor (i.e. current that flows in the opposite direction to the loop current) after the loop current stops. A second diode is interposed in series with the second inductor to provide appropriate voltage offsets in the circuit and to prevent the first inductor from being shorted to ground through the second inductor.
    Type: Grant
    Filed: January 13, 2003
    Date of Patent: October 26, 2004
    Assignee: Linear Technology Corporation
    Inventor: Dale R. Eagar
  • Polyphase PWM regulator with high efficiency at light loads
    Patent number: 6803752
    Abstract: A multi-phase multi-channel voltage regulator having high efficiency at light loads is provided. The regulator increases efficiency at light loads by shutting down a select channel of the regulator. In addition, the regulator may place remaining channels in Burst Mode.
    Type: Grant
    Filed: February 14, 2000
    Date of Patent: October 12, 2004
    Assignee: Linear Technology Corporation
    Inventor: Wei Chen
  • High voltage MOS transistor with gate extension
    Patent number: 6797549
    Abstract: A high voltage MOS transistor with a gate extension that has a reduced electric field in the drain region near the gate is provided. The high voltage MOS transistor includes a first and second gate layers, and a dielectric layer between the gate layers. The first and second gate layers are electrically coupled together and form the gate of the transistor. The second gate layer extends over the drain of the transistor above the dielectric and gate oxide layers to form the gate extension. The gate extension reduces the peak electric field in the drain by providing a wide area for the voltage to drop between the drain and the gate of the transistor. The dielectric layer also reduces the peak electric field in the drain near the gate by providing insulation between the gate and the drain. A lower electric field in the drain reduces the impact generation rate of carriers.
    Type: Grant
    Filed: October 15, 2002
    Date of Patent: September 28, 2004
    Assignee: Linear Technology Corporation
    Inventor: Francois Hebert
  • Circuits and methods for a variable over sample ratio delta-sigma analog-to-digital converter
    Patent number: 6795007
    Abstract: Circuits and methods for a delta-sigma analog-to-digital converter having a variable oversample ratio to produce a constant fullscale output at reduced circuit complexity, die area, and power dissipation are provided. The circuits and methods consist of scaling the digital input to the digital filter with a decoder whose size depends on the number of oversample ratios allowed by the analog-to-digital converter. The digital filter is implemented as a comb filter having a cascade of N integrators and N differentiators, where N is the order of the digital filter. The size of the differentiators is equal to the number of bits used as output for the analog-to-digital converter, which is smaller than the size of the integrators and the number of bits produced by the digital filter.
    Type: Grant
    Filed: October 28, 2003
    Date of Patent: September 21, 2004
    Assignee: Linear Technology Corporation
    Inventor: Michael Keith Mayes
  • Circuits and methods for synchronizing non-constant frequency switching regulators with a phase locked loop
    Patent number: 6774611
    Abstract: Methods for synchronizing non-constant frequency switching regulators with a phase locked loop are disclosed. The methods enable non-constant frequency switching regulators to be synchronized with a phase locked loop to achieve constant frequency operation in steady state while retaining the advantages of non-frequency operation to improve transient response and operate over a wider range of duty cycles. In addition, the methods enable multiple non-constant frequency regulators to be synchronized and operated in parallel to deliver higher power levels to the output than a single switching regulator.
    Type: Grant
    Filed: July 15, 2002
    Date of Patent: August 10, 2004
    Assignee: Linear Technology Corporation
    Inventors: Christopher B. Umminger, Randy G. Flatness
  • High-speed, current driven latch
    Publication number: 20040150450
    Abstract: A high-speed, current-driven latch is provided. The latch conducts a current and includes an output, a SET circuit and a RESET circuit. The output is variable between a first state and a second state. The SET circuit conducts the current present in the latch at the first state such that the SET circuit is maintained close to a level required to change the output of the transistor from the first to the second level, and the RESET circuit conducts the current at the second level such that the RESET circuit is close to a level required to change the output of the transistor from the second level to the first level.
    Type: Application
    Filed: January 20, 2004
    Publication date: August 5, 2004
    Applicant: Linear Technology Corporation
    Inventor: Karl Edwards