Abstract: Described embodiments provide for, in a receiver circuit employing a data latch, circuitry to adjust trim offset of the data latch to account for latch functional features (e.g., hysteresis and metastability) that may interact with trim of the latch. In accordance with the described embodiments, a trim procedure runs in a pre-selected directions of offset voltage ramp in order to average out the effect of hysteresis and metastability on the final trim offset choice. Different thresholds for accumulated slicer “0” and “1” discrimination of the circuitry to adjust trim offset allows for significant reduction in the number of trim runs, accelerating the slicers' trim process allowing for relatively quick determination of trim offset whenever the slicers are idle.

Abstract: A receiving coil apparatus for use in an electromagnetic energy transfer system includes multiple conductive loops and a switching circuit connected with the conductive loops. The switching circuit is configured to control an electrical center of the receiving coil apparatus as a function of at least one control signal. A controller connected with the switching circuit is configured to generate the control signal for controlling an alignment of the electrical center of the receiving coil apparatus with an electromagnetic field so as to enhance an amount of energy transferred to the receiving coil apparatus from the electromagnetic field.

Abstract: A decision feedback equalization slicer for ultra-high-speed backplane Serializer/Deserializer (SerDes) with improved latch sensitivity. A first regeneration stage can be configured in association with a second regeneration stage to compensate for channel impairment such as inter-symbol interference due to channel loss, reflections due to impedance mismatch, and cross-talk interference from neighboring electrical channels. The first regeneration stage includes two first stage slicers corresponding to a set of speculative decision (+h1 and ?h1). A multiplexer can be placed at an input port of the second regeneration stage to select the set of speculative decision based on previous decision in order to save hardware and power. The DFE slicer samples the input signal, regenerates the sampled data, stores the data on storage element like RS-latch or flip-flop, and presets the regeneration nodes to high or low values in preparation for sampling the next input data.

Abstract: An apparatus comprising a memory and a controller. The memory is configured to process a plurality of read/write operations. The memory comprises a plurality of memory modules each having a size less than a total size of the memory. The controller is configured to salvage data stored in a failed page of the memory determined to exceed a maximum number of errors. The controller copies raw data stored in the failed page. The controller identifies locations of a first type of data cells that fail erase identification. The controller identifies locations of a second type of data cells that have program errors. The controller flips data values in the raw data at the locations of the first type of data cells and the locations of the second type of data cells. The controller is configured to perform error correcting code decoding on the raw data having flipped data values. The controller salvages data stored in the failed page.

Abstract: System and method for dynamic storage tiering are disclosed. A storage hot-spot in a first storage pool is detected. A first point-in-time copy of a virtual volume including the storage hot-spot is created in a second storage pool according to the detecting. Write requests directed to the virtual volume are redirected to the second storage pool. When decreased I/O activity directed to the storage hot-spot in the second storage pool is detected, the point-in-time copy in the second storage pool is reintegrated into at least one of a second point-in-time copy or the virtual volume.

Abstract: Systems and methods for image processing may perform one or more operations including, but not limited to: receiving raw image data from at least one imaging device; computing at least one image depth distance from the raw image data; computing one or more image validity flags from the raw image data; generating at least one data validity mask from the one or more image validity flags; determining a background imagery estimation from at least one image depth distance; generating at least one foreground mask from the background imagery estimation and the at least one image depth distance; generating at least one region-of-interest mask from the data validity mask and the foreground mask; and generating filtered raw image data from the raw image data and at least one region of interest mask.

Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for protecting portions of data sets during data processing.

Abstract: In a data storage system in which a host system transfers data to a data storage controller having cache memory, the data storage controller can use a designated field of each of several cache data blocks, such as an application (APP) field, to contain protection information from fields of a host data block, such as the guard (GRD) and reference (REF) fields as well as the APP field.

Abstract: An apparatus for measuring cross-talk in an array reader magnetic storage system includes an array reader with multiple read heads operable to read data from a magnetic storage medium, a first preamplifier connected to a first read head, a second preamplifier connected to a second read head, and a cross-talk measurement circuit connected to the first preamplifier and to the second preamplifier, operable to measure cross-talk between a first signal from the first read head and a second signal from the second read head.

Abstract: A RAID storage system serializes data blocks to be stored in a RAID storage array and uses a primary map table and a number of secondary map tables to relate host addresses to logical block addresses in the storage array. Secondary map tables and other metadata can be cached from the storage array. The dual or two-tier map scheme and metadata caching promote scalability.

Abstract: A system includes a processor configured to read information from a plurality of memory cells. The processor initiates a first read of raw data from a group of memory cells using a first reference voltage. The processor also initiates a second read of raw data from the group of memory cells using a second reference voltage different from the first reference voltage. The processor further compares the first read to the second read to identify memory cells read with a bit value that changes between the first and second reads. The processor also assigns the memory cells read with a bit value that changes between the first and second reads to a region associated with the second reference voltage. The processor further counts the number of cells read with a bit value that changes to generate a histogram corresponding to soft information for the group of memory cells.

Abstract: Aspects of the disclosure pertain to methods and systems that are configured to handle excessive read noise in soft read systems. In an implementation, a method includes determining a number of unexpected patterns of a soft read of a memory cell after a soft decoding failure. The method also includes determining whether the number of unexpected patterns is greater than a threshold number of unexpected patterns. When it is determined that the number of unexpected patterns is greater than the threshold number of unexpected patterns, the method at least one of: performing at least one more soft read of the memory cell with a larger read voltage spacing than an initial read that produced the soft decoding failure; and discarding a result of one or more soft reads of the memory cell and utilizing a remainder of results of respective other soft reads of the memory.

Abstract: An apparatus includes an error correction code circuit and an error correction code selection circuit. The error correction code circuit may be configured to encode and decode data using any of a plurality of error correction codes. The error correction code selection circuit may be configured to control which of the plurality of error correction codes is used by the error correction code circuit to encode and decode data responsive to one or more reliability statistics and predetermined data characterizing distribution properties of each of the plurality of error correction codes.

Abstract: Systems and method relating generally to data processing, and more particularly to systems and methods for scaling messages in a data decoding circuit.

Abstract: An apparatus includes a plurality of memory dies and a controller. The controller may be communicatively coupled to the plurality of memory dies and configured to utilize multiple copies of a root record containing system data during a boot-up process. The multiple copies of the root record are stored using at least two of the plurality of memory dies.

Abstract: A storage controller coupled to a host computer is dynamically configured by a device driver executing in the host computer. The storage controller manages a logical volume for the host using a set of flash-based storage devices arranged as a redundant array of inexpensive disks (RAID). The device driver identifies a RAID type for the logical volume and a queue depth from a stream of I/O commands. For a logical volume in RAID 0, the device driver compares the queue depth to a threshold value and configures the storage controller to process the stream of I/O commands with a first path or an alternative path based on a result of the comparison. For a logical volume in RAID 5, the device driver performs a similar comparison and uses the result to direct the storage controller to use a write back or a write through mode of operation.

Abstract: An apparatus comprising a memory and a controller. The memory is configured to process a plurality of read/write operations. The memory comprises a plurality of memory unit granularities each having a size less than a total size of the memory. The controller is configured to process a plurality of I/O requests to the memory units of the memory that are not marked as bad on a memory unit list. The controller is configured to track a plurality of bad blocks of the memory. The controller is configured to determine which of the memory units to mark as bad based on a test of whether a unit of memory larger than a block of the memory has failed. The test is based on a threshold of the bad blocks in the unit of memory.

Abstract: Systems and methods provide zone management for devices in a Serial Attached Small Computer System Interface (SAS) topology. In one embodiment, a zone management device stores a zone map that identifies an initial zone of a device in the topology. The management device detects changes in the topology, and identifies a current zone of the device subsequent to the change in the topology. The management device compares the zone map for the device to the current zone to identify a change in the zone of the device, and generates a message for an expander in the topology based on the change in the zone. The management device then transmits the message to the expander to restore the zone of the device to the initial zone.

Abstract: An apparatus for measuring cross-talk in an array reader magnetic storage system includes an array reader with multiple read heads operable to read data from a magnetic storage medium, a first preamplifier connected to a first read head, a second preamplifier connected to a second read head, and a cross-talk measurement circuit connected to the first preamplifier and to the second preamplifier, operable to measure cross-talk between a first signal from the first read head and a second signal from the second read head.

Abstract: Systems, methods, devices, circuits for data processing, and more particularly to systems and methods for processing skew tolerant processing of data derived from multiple read heads.