Abstract: An apparatus having a circuit and an interface to a nonvolatile memory is disclosed. The circuit is configured to (i) perform one or more attempts of a soft-decision decode of data stored in the nonvolatile memory, where soft-decision decode uses a plurality of log likelihood ratio values stored in a table, (ii) generate one or more adjusted log likelihood ratio values by adding a constant value to one or more of the log likelihood ratio values in response to a failure to decode the data using the log likelihood ratio values and (iii) re-decode the data using the adjusted log likelihood ratio values.

Abstract: A bonding pad arrangement and method of bonding a flip-chip semiconductor device to a substrate using copper pillars and solder to join die pads on the flip-chip to substrate pads on the substrate. Each substrate pad has an offset from a respective die pad at specific temperature, the offset for each of the substrate pads is substantially the same, and the offset is determined as a function of the size of the flip-chip device, a difference between a solidification temperature of the solder and the specific temperature, and a difference between a coefficient of thermal expansion of the flip-chip device and a coefficient of thermal expansion of the substrate. Alternatively, the offset for each of the substrate pads is the above-determined offset scaled as a function of a distance the respective die pad is from the centroid of the device.

Abstract: Systems, methods, devices, circuits for data processing, and more particularly to systems and methods for processing servo data using two or more sensing heads.

Abstract: Systems, methods, devices, circuits for data processing, and more particularly to systems and methods for reporting a synchronization indication and for applying a synchronization window. As an example, a system is discussed that includes: a head assembly including a first read head and a second read head; a down track distance calculation circuit operable to calculate a down track distance between the first read head and the second read head; and a synchronization mark detection circuit. The synchronization mark detection circuit is operable to: assert a synchronization mark window based at a location based at least in part on the down track distance; query a first data set derived from the first read head for a synchronization mark occurring within the synchronization mark window; and query a second data set derived from the second read head for the synchronization mark occurring within the synchronization mark window.

Abstract: Systems, methods, devices, circuits for data processing, and more particularly to systems and methods for determining a down track distance between two or more read heads on a read/write head assembly.

Abstract: A bonding apparatus and method of bonding copper bond wires to bond pads on an integrated circuit devices attached to a substrate. A heater block heats the devices and substrate prior to and during wire bonding. A clamp presses the substrate down onto the heater block during wire bonding and thereby forms a region of the substrate isolated from the remainder of the substrate. A bonder head creates ball bonds as it attaches one end of the bond wires to the bond pads on the devices within the isolated region. The bonder head also attaches the other end of the bond wires to substrate pads adjacent the devices being wire bonded. To prevent corrosion of the ball bonds, a gas source floods the substrate and the attached devices that have not yet wire bonded with a purge gas while the heater block heats the substrate and the attached devices.

Abstract: A multi-stage system and method for correcting intersymbol interference is disclosed. The system includes a first estimation module configured to sample an input signal to produce a first set of estimated data bits. The system also includes a second estimation module configured to sample the input signal phase shifted by a predetermined phase shift unit to produce a second set of estimated data bits, wherein the second set of estimated data bits are produced at least partially based on the first set of estimated data bits and at least one pre-cursor coefficient.

Abstract: Phase detectors and timing recovery techniques that do not require error latches nor oversampling of the received input data are disclosed. The phase detection method includes separating an input signal into N consecutive data bits; comparing at least two consecutive data bits within the N consecutive data bits; estimating a data bit value for each of the N consecutive data bits; and determining a phase difference based on a data bit pattern formed by the data bit values of the N consecutive data bits and the comparison of the at least two consecutive data bits within the N consecutive data bits.

Abstract: A data processing system includes a likelihood input operable to receive encoded data, a decoder operable to apply a decoding algorithm to likelihood values for the received encoded data and to yield a decoded output, and a decoder input initialization circuit operable to generate new decoder input values based in part on the likelihood values for the received encoded data after the likelihood values for the received encoded data have failed to converge in the decoder.

Abstract: An apparatus comprising a memory and a controller. The memory is configured to process a plurality of read/write operations. The memory comprises a plurality of memory modules. Each memory module has a size less than a total size of the memory. The controller is configured to write user data using a plurality of threshold voltages. The data considered hot-read data is written using a first voltage threshold. The data not considered hot-read data is written using a second voltage threshold. The first voltage threshold reduces an impact on endurance of the memory.

Abstract: An apparatus comprising a memory and a controller. The memory is configured to process a plurality of read/write operations. The memory comprises a plurality of memory modules. Each memory module has a size less than a total size of the memory. The controller is configured to (i) classify data from multiple blocks of the memory as hot-read data or non hot-read data, (ii) aggregate the hot-read data to dedicated blocks, and (iii) select a type of error correcting code to protect the hot-read data in the dedicated blocks. The aggregation reduces an impact on endurance of the memory.

Abstract: Systems and method relating generally to data processing, and more particularly to systems and methods for data synchronization and detection.

Abstract: A communication channel structure and a decoding method supported by such a communication channel structure are disclosed. Such a communication channel includes a digital filter configured for filtering an input signal and two quantizer configured for quantizing the filtered signal. A first quantizer is utilized to quantize the filtered signal to produce a first quantized sample having a first precision and a second quantizer is utilized to quantize the filtered signal to produce a second quantized sample having a second precision, wherein the second precision is different from the first precision. The communication channel also includes an iterative decoder configured for utilizing the first quantized sample for a first global iteration of a decoding process and utilizing the second quantized sample for at least one subsequent global iteration of the decoding process.

Abstract: Systems and method relating generally to solid state memory, and more particularly to systems and methods for recovering data from a solid state memory.

Abstract: A data storage system identifies analog-to-digital conversion samples with amplitude below a certain threshold. Remaining samples are grouped according to phase into one or more quadrants. A multi-coordinate with overlapping quadrants is used to further differentiate sample points. The system then computes an average phase for zero phase start estimation.

Abstract: An apparatus includes a controller and an adaptive error correction code decoder. The controller may be configured to read data from and write data to a memory device. The controller may be further configured to write data in a two-step process, which includes (i) after writing data to a least significant bit (LSB) page, checking the data stored in the LSB page using a first strength error correction code (ECC) decoding process and (ii) after writing data to a most significant bit (MSB) page associated with the LSB page, checking the data stored in both the LSB and MSB pages using a second strength error correction code (ECC) decoding process.

Abstract: Applications that use non-volatile random access memory (NVRAM), such as those that apply file system journal writes and database log writes where write operations apply data sequentially over the NVRAM, map the available capacity of the NVRAM in a virtual address space without compromising performance. The NVRAM is segmented into regions with multiple such regions fitting within a volatile RAM element accessible to the application and the NVRAM. One or more regions are loaded in the volatile RAM and reflected in page tables that reference the regions. The page tables are managed on a host computer executing the application. One region space in the volatile RAM is unused and available for transferred information. Mechanisms are provided for dynamically transferring regions and interfacing with the host computer. As the application sequentially accesses information in the stored regions, older regions are removed and new regions loaded from NVRAM to the volatile RAM.

Abstract: A method of operating a multi-reader two-dimensional magnetic recording system includes determining a position of a multi-reader head of the multi-reader two-dimensional magnetic recording system, determining an areal density push according to the position of the multi-reader head, and performing an operation to read data from or write data to a magnetic recording medium according to the areal density push.

Abstract: Systems and method relating generally to solid state memory, and more particularly to systems and methods for reducing errors in a solid state memory.

Abstract: A method for enhancing read performance in an ARMR system includes: obtaining CTS information for a plurality of readers in a multi-reader head of the ARMR system, the CTS information defining a relationship between skew angle and CTS between respective combinations of subsets of the readers; determining, as a function of the CTS information, a given one of the combinations of subsets of the readers which provides enhanced read performance among a total number of combinations of subsets of the readers for each of a plurality of skew angles; and selecting, for subsequent processing by a read channel in the ARMR system, the given one of the combinations of subsets of the readers determined to provide enhanced read performance for a given one of the skew angles corresponding to a zone in which the multi-reader head is operating.