Patents Assigned to LSI Corporation
  • Publication number: 20150279398
    Abstract: Described embodiments provide a magnetic mass storage device with a system clock phase-locked to servo address marks on the magnetic disk. A head sequentially reads multiple adjacent servo address marks in a spiral track of servo address marks. When a servo address mark detector detects a mark, the count value of a counter driven by the system clock is sampled and held by a latch. A system clock synthesizer calculates differences in value between successively sampled count values from the latch, averages the differences in value to create an average difference value, and normalizes a difference between the average difference value and a target value to create a phase error value. The phase of the system clock is updated using the phase error value.
    Type: Application
    Filed: April 3, 2014
    Publication date: October 1, 2015
    Applicant: LSI Corporation
    Inventors: Xiangdong Fan, Songtao Chen
  • Publication number: 20150269097
    Abstract: The disclosure is directed to a system and method of managing memory resources in a communication channel. According to various embodiments, incoming memory slices associated with a plurality of data sectors are de-interleaved and transferred sequentially through a buffer to a decoder for further processing. To prevent buffer overflow or degraded decoder performance, the memory availability of the buffer is monitored, and transfers are suspended when the memory availability of the buffer is below a threshold buffer availability.
    Type: Application
    Filed: March 31, 2014
    Publication date: September 24, 2015
    Applicant: LSI Corporation
    Inventors: Ku Hong Jeong, Qi Zuo, Shaohua Yang, Kaitlyn T. Nguyen
  • Publication number: 20150269304
    Abstract: A system is described that analyzes timing of a design and conditionally replaces values of a cell to lower total power within circuit paths having a positive timing margin. The system includes a computing device that includes a memory for storing modules and a processor that is operable to execute the modules. The modules cause the processor to conditionally replace a first semiconductor characteristic with a second semiconductor characteristic associated with a cell in a path of a circuit design and estimating a delay and a slack of the path based upon the first semiconductor characteristic. The modules also cause the processor to determine whether the second semiconductor characteristic causes a timing violation with respect to the path and causes conditional replacement of the second semiconductor characteristic with a third semiconductor characteristic until the timing violation is removed.
    Type: Application
    Filed: March 21, 2014
    Publication date: September 24, 2015
    Applicant: LSI Corporation
    Inventors: Bruce E. Zahn, David M. Ratchkov, Benjamin Mbouombouo
  • Publication number: 20150269990
    Abstract: A memory includes a number of storage elements connected to a pair of bit-lines, a bit-line pre-charging circuit, a sense amplifier connected to the pair of bit-lines through a column-select switch, a transition detection circuit connected to an output of the sense amplifier, and a local pre-charge control circuit connected to the transition detection circuit and having a local pre-charge control signal output connected to the bit-line pre-charging circuit.
    Type: Application
    Filed: March 18, 2014
    Publication date: September 24, 2015
    Applicant: LSI Corporation
    Inventors: Rahul Sahu, Dharmendra Kumar Rai
  • Publication number: 20150268871
    Abstract: An apparatus having a processor and an interface to a nonvolatile memory having a plurality of blocks is disclosed. The processor is configured to (i) monitor a number of reads since a respective erase in at least one of the blocks in the nonvolatile memory, (ii) move a page from a first block to a second block in response to the number of reads exceeding a first threshold where the first block is partially programmed and (iii) move the page from the first block to the second block in response to the number of reads exceeding a second threshold where the first block is fully programmed. The first threshold is less than the second threshold.
    Type: Application
    Filed: April 2, 2014
    Publication date: September 24, 2015
    Applicant: LSI Corporation
    Inventors: Nanshan Shu, Peng Xu, Zhimin Dong, Yingyi Ju, Jiangang Wu
  • Publication number: 20150269054
    Abstract: A data processing system includes a number of processor cores each having a trace interface with an address signal carrying program addresses being executed, a processor core identification circuit connected to the trace interfaces and operable to replace a portion of some of the program addresses with a processor core identification that identifies which of the processor cores provided the program addresses, and an execution trace buffer operable to store the program addresses associated with non-sequential execution in the processor cores. At least some of the program addresses include the processor core identification along with address bits.
    Type: Application
    Filed: March 18, 2014
    Publication date: September 24, 2015
    Applicant: LSI Corporation
    Inventors: Srinivasa Rao Kothamasu, Romeshkumar Bharatkumar Mehta
  • Publication number: 20150261636
    Abstract: Methods and systems for generating data transformations to improve ROM yield and programming time. A bit flip register can be configured in association with the ROM and a binary string can be read into the bit flip register on reset. Subsequently, data output from the ROM can be selectively complemented utilizing a content of the bit flip register and the content of the bit flip register can be programmed into the ROM in order to reduce programming time for each ROM. A defective cell can be tolerated by selectively flipping a column with respect to the defective cell to improve yield. A built-in self-test (BIST) engine that generates addresses up to and including content of an address limiting register can be employed to limit the ROM access to a programmed part during testing in order to tolerate defects in any unused location.
    Type: Application
    Filed: March 17, 2014
    Publication date: September 17, 2015
    Applicant: LSI Corporation
    Inventor: Sreejit Chakravarty
  • Publication number: 20150263848
    Abstract: Described embodiments provide for, in a clock and data recovery (CDR) circuit, detection of loss of acquisition and CDR restarting with corrective integral accumulator register seeding and gearshift restarting. In described embodiments, a mechanism is employed to cause faster loss of lock condition if the CDR circuit directed on an incorrect acquisition trajectory, actual loss of CDR lock is then detected, and CDR acquisition is recovered with corrective integral accumulator seeding.
    Type: Application
    Filed: April 21, 2014
    Publication date: September 17, 2015
    Applicant: LSI Corporation
    Inventors: Mohammad S. Mobin, Weiwei Mao, Chintan M. Desai, Ye Liu
  • Publication number: 20150262710
    Abstract: Methods and systems for reducing memory test time utilizing a serial per march element communicating architecture. A small number of slow speed signals can be configured between a BIST wrapper and a BIST controller to transfer information in accordance with a BIST sequence that includes a number of march elements. An information transfer protocol can be implemented between the BIST wrapper and the BIST controller to transfer Information with respect to each march element that includes a number of BIST operations, address sequencing information, and data pattern. A command register can be loaded utilizing the slow speed signals and slow speed clock and content of the command register can be decoded. An encoded BIST operation can then be executed once for each BIST operation per march element. The serial per march element communicating architecture reduces test time as a communication overhead and a requirement for high speed wires are eliminated.
    Type: Application
    Filed: March 14, 2014
    Publication date: September 17, 2015
    Applicant: LSI Corporation
    Inventor: Sreejit Chakravarty
  • Publication number: 20150262949
    Abstract: A process to form metal pillars on a flip-chip device. The pillars, along with a layer of solder, will be used to bond die pads on the device to respective substrate pads on a substrate. A photoresist is deposited over the device and first openings in the photoresist are formed. Metal layers are formed by electroplating metal into the first openings for a first time period. Then the photoresist is patterned to form second openings having a smaller diameter than the first openings. Narrow pillars are formed by electroplating metal into the second openings for a second time period during which the metal is also added to the metal layers in the first openings to form wide pillars having substantially the same height as the narrow pillars. The photoresist is then removed along with conductive layers on the device used as part of the plating process.
    Type: Application
    Filed: April 23, 2014
    Publication date: September 17, 2015
    Applicant: LSI Corporation
    Inventors: John W. Osenbach, Steven D. Cate
  • Publication number: 20150262592
    Abstract: Systems, methods, devices and circuits for data amplification, and more particularly systems and methods for characterizing distortion introduced during data amplification. In some cases, an amplifier modeling circuit is discussed that receives a preamplifier status input from a preamplifier circuit; applies a vector fitting algorithm to the preamplifier status to yield a pole value; determines that the pole value is greater than unity; and replaces the pole value with an inverse of the pole value when the pole value is greater than unity.
    Type: Application
    Filed: March 18, 2014
    Publication date: September 17, 2015
    Applicant: LSI Corporation
    Inventor: Xiufeng Song
  • Publication number: 20150262950
    Abstract: A process to form metal pillars on a flip-chip device. The pillars, along with a layer of solder, will be used to bond die pads on the device to respective substrate pads on a substrate. A photoresist is deposited over the device and a first set of die pads on the device are exposed by forming openings of a first diameter in the photoresist. Pillars of the first diameter are formed by electroplating metal onto the exposed die pads. Then a second photoresist deposited over the first photoresist covers the pillars of the first diameter. Openings of a second diameter are formed in the first and second photoresists to expose a second set of die pads. Pillars of the second diameter are formed by electroplating metal onto the exposed die pads. The photoresists are then removed along with conductive layers on the device used as part of the plating process.
    Type: Application
    Filed: April 23, 2014
    Publication date: September 17, 2015
    Applicant: LSI Corporation
    Inventors: Steven D. Cate, John W. Osenbach
  • Publication number: 20150256364
    Abstract: Described embodiments provide for de-coupling between adaptation of decision feedback equalizer (DFE) filter taps and transmitter (TX) post cursor filtering in group delay (GD)-based adaptation. Consequently, an excessive build-up of transmitter post cursor effects and its excessive equalization cancellation by the DFE may be substantially reduced or eliminated. By breaking this coupling, a transmitter does not over equalize a signal, the DFE does not attempt to “undo” the over equalization, and a variable gain amplifier (VGA) in the receiver front end data path generally does not apply gain to amplify the signal back again due to the reduced DC level. GD-based TX post cursor adaptation may reduce over equalization effect and hence save power and increase performance by not over equalizing the signal.
    Type: Application
    Filed: April 9, 2014
    Publication date: September 10, 2015
    Applicant: LSI Corporation
    Inventors: Mohammad S. Mobin, Vladimir Sindalovsky
  • Publication number: 20150255101
    Abstract: A method of mitigating an effect of track misregistration on read performance in a system comprising an array-reader includes determining an estimated off-track condition, selecting translation coefficients based on the estimated off-track condition, determining updated equalizer coefficients by applying the translation coefficients to native equalizer coefficients, and applying the updated equalizer coefficients to signals received from the array-reader to output a read signal.
    Type: Application
    Filed: April 28, 2014
    Publication date: September 10, 2015
    Applicant: LSI Corporation
    Inventors: George Mathew, Jongseung Park, Eui Seok Hwang
  • Publication number: 20150256196
    Abstract: An apparatus having a circuit and an interface to a nonvolatile memory is disclosed. The circuit is configured to (i) read a plurality of bits in a read channel of the nonvolatile memory. The bits are encoded with a polar code. The circuit is also configured to (ii) generate a plurality of probabilities based on a plurality of log likelihood ratio values of the read channel and (iii) decode the bits based on the probabilities.
    Type: Application
    Filed: March 19, 2014
    Publication date: September 10, 2015
    Applicant: LSI Corporation
    Inventors: AbdelHakim S. Alhussien, Erich F. Haratsch, Yue Li
  • Publication number: 20150255109
    Abstract: Systems and methods for magnetoresistive asymmetry estimation may include, but are not limited to, operations for: receiving a magnetic read head transducer output; computing a mean value of the magnetic read head transducer output; computing a median value of the magnetic read head transducer output; and applying a correction coefficient to a magnetic read head detector input according to at least the mean value of the magnetic read head transducer output and the median value of the magnetic read head transducer output.
    Type: Application
    Filed: March 7, 2014
    Publication date: September 10, 2015
    Applicant: LSI Corporation
    Inventors: Bruce A. Wilson, Nayak Ratnakar Aravind, Haitao Xia
  • Publication number: 20150255113
    Abstract: Systems and methods for resource allocation for a large sector format processing may include, but are not limited to, operations for: determining non-convergence of a magnetic disc sub-sector of a first magnetic disc sector within a processing time frame allocated to the magnetic disc sub-sector; determining a convergence of a second magnetic disc sector occurring in less time than a processing time frame allocated to the second magnetic disc sector; and processing the magnetic disc sub-sector during a portion of the processing time frame allocated to the second magnetic disc sector remaining after processing of the second magnetic disc sector.
    Type: Application
    Filed: May 2, 2014
    Publication date: September 10, 2015
    Applicant: LSI Corporation
    Inventors: Shu Li, Fan Zhang, Jun Xiao
  • Publication number: 20150256363
    Abstract: An N-way parallel, unrolled decision feedback equalizer for a SerDes receiver can convert between four-tap PAM-2 and two-tap PAM-4 mode, maximizing hardware through the use of mode control multiplexers. Each of N interleaved parallel branches includes an ISI correction stage for generating a partial result approximating intersymbol interference and comparing the partial result to a threshold, a carry look-ahead stage for generating a second partial result based in part on previously generated partial results, and a decision feedback stage for generating a final decision based on previous branches. Mode control multiplexers can select from PAM-2 and PAM-4 operating modes, PAM-2 and MAP-4 inputs at various stages, or from single-bit PAM-2 and two-bit PAM-4 outputs. ISI correction can additionally be reformulated to incorporate comparing raw input symbols to a combination of approximated ISI and a threshold.
    Type: Application
    Filed: March 27, 2014
    Publication date: September 10, 2015
    Applicant: LSI Corporation
    Inventors: Volodymyr Shvydun, Adam B. Healey, Chaitanya Palusa
  • Publication number: 20150249555
    Abstract: In described embodiments, process, voltage, temperature (PVT) compensation in a serializer/deserializer (SerDes) device employs a closed loop adaptation compensation that is incorporated into the SerDes receiver adaptation process. A detection method, where the adapted decision feedback equalizer (DFE) target level (e.g., tap H0) is monitored, employs this DFE target level when implementing a closed loop variable gain amplifier adaptation. The DFE target level in conjunction with the VGA level is used to control the PVT setting to maintain target SerDes data path gain by detecting aPVT corner condition. The detected PVT corner condition is employed to generate a control signal to further adjust the LEQ and DFE data path differential pair gain as required by the PVT condition.
    Type: Application
    Filed: April 3, 2014
    Publication date: September 3, 2015
    Applicant: LSI Corporation
    Inventors: Mohammad S. Mobin, Weiwei Mao, Chintan M. Desai, Freeman Y. Zhong, Ye Liu
  • Publication number: 20150243321
    Abstract: An exemplary hard disk (HD) track has a full overhead section followed by user sections interleaved with intervening partial overhead sections that are too short for an HD drive (HDD) to attain sufficient timing lock using only one partial overhead section, but long enough for the drive to attain sufficient timing lock using multiple partial overhead sections to read user data from the user section immediately following the partial overhead section where sufficient timing lock is attained. The drive begins, but does not finish, attaining timing lock based on the first partial overhead section, but the drive does finish attaining timing lock based on the last partial overhead section. The drive can also read user data in subsequent user sections by maintaining or re-attaining sufficient timing lock using each successive partial overhead section. Increased user data storage is achieved without significantly impacting average latency of HDD read sessions compared to conventional HD drives.
    Type: Application
    Filed: March 20, 2014
    Publication date: August 27, 2015
    Applicant: LSI Corporation
    Inventors: Kurt J. Worrell, Jason D. Byrne, Scott M. Dziak