Patents Assigned to LSI Logic Corporation
-
Patent number: 6973407Abstract: The present invention provides a method for capturing data suitable for creating a Serial ATA eye diagram. A Serial ATA host controller including a first and a second Serial ATA ports is powered up, where receive lines of the first Serial ATA port are short-circuited to receive lines of the second Serial ATA port, and the first Serial ATA port is communicatively coupled to a Serial ATA drive. An initialization pattern from the Serial ATA drive is received by the first and the second Serial ATA ports. An ALIGN/SYNC pattern is transmitted over transmit lines of the second Serial ATA port. Data transmitted over the transmit lines of the second Serial ATA port is captured using a high impedance differential probe and an oscilloscope. The captured data may be used to create a Serial ATA eye diagram for the second Serial ATA port on the oscilloscope.Type: GrantFiled: May 13, 2004Date of Patent: December 6, 2005Assignee: LSI Logic CorporationInventor: Moby Abraham
-
Patent number: 6973441Abstract: The present invention is a method for operating a computer-based accounts payable system. The user inputs a bill that includes a billing code. The system then determines whether the billing code is present in the budget database. If the billing code is present in the budget database, the system approves payment of an amount associated with the billing code in the budget database. If the billing code is not present in the budget database, the system approves payment of a budget amount associated with the billing code in a default budget database. In the preferred embodiment, the system also checks whether a particular task has been completed before approving payment of said bill, and checks to insure that a previous bill covering the same task has not been paid previously.Type: GrantFiled: January 10, 2001Date of Patent: December 6, 2005Assignee: LSI Logic CorporationInventor: Sandeep Jaggi
-
Patent number: 6973221Abstract: A method and apparatus for reducing block related artifacts in video are disclosed. A boundary is defined in a video frame between at least two or more sub-blocks where each of the sub-blocks contains a predetermined number of pixels. Pixels adjacent to the boundaries of the sub-blocks may be filtered to reduce blocking artifacts in the video. Pixel video values such as luma and chroma values may be utilized as input values to an anti-block filter. Average mean and average variance of the pixel video values in a sub-block are used to determined when anti-block filtering is applied. Pixels adjacent to the sub-block boundaries are filtered with an anti-block filtering algorithm in the event a predetermined condition is satisfied where the condition may be based upon the calculated average mean and average variance values. The filtering algorithm may include recalculating a pixel video value for pixels adjacent the sub-block boundaries.Type: GrantFiled: December 14, 1999Date of Patent: December 6, 2005Assignee: LSI Logic CorporationInventor: Ning Xue
-
Patent number: 6972840Abstract: Optical emission spectra from a test wafer during a plasma process are measured using a spectrometer. The plasma charging voltage retained by (detected by) the test wafer is measured after the process step is completed. The emission spectra are correlated with the plasma charging voltage to identify the species contributing to the plasma charging voltage. The optical emission spectra are monitored in real time to optimize the plasma process to prevent plasma charging damage. The optical emission spectra are also monitored to control the plasma process drift.Type: GrantFiled: October 6, 2003Date of Patent: December 6, 2005Assignee: LSI Logic CorporationInventors: Shiqun Gu, Peter Gerard McGrath, Ryan Tadashi Fujimoto
-
Patent number: 6973524Abstract: The present invention is directed to an interface. An interface system suitable for coupling a first bus interface controller with a second bus interface controller includes a first bus interface controller and a second bus interface controller in which the second bus interface controller is coupled to the first bus interface controller via an interface. The interface includes a command queuing interface suitable for enqueueing a transaction, a command completion interface suitable for reporting transaction completion and a data transfer interface suitable for transferring data.Type: GrantFiled: December 14, 2000Date of Patent: December 6, 2005Assignee: LSI Logic CorporationInventors: Richard L. Solomon, Timothy E. Hoglund
-
Publication number: 20050264995Abstract: A system and method for cooling a series of heat generating devices arrayed sequentially in the axis of flow for a cooling medium. An inlet manifold contains a stepped chamber whereby cool air is apportioned to several chambers, each chamber containing a heat generating device. An outlet manifold contains a similar stepped chamber whereby heated air is exhausted from the heat generating device. In an embodiment of a disk array, each chamber may hold one or more disk drives. Further, the manifold system may also serve as a mounting bracket for the disk drives.Type: ApplicationFiled: May 28, 2004Publication date: December 1, 2005Applicant: LSI Logic CorporationInventor: George Hanson
-
Publication number: 20050265438Abstract: In contrast to prior are solutions that conduct an averaging operation to estimate metrics related to a communications channel such as a signal-to-noise ratio, the present invention selects a particular value such as a minimum, maximum, or median value from a distribution of values collected over a selected interval. Selecting a particular value from the distribution of values facilitates a more accurate characterization process and increased data throughput. To reduce the processing burden associated with selecting a particular value, the present invention provides a set of cascaded value selection queues that each selects a particular value from the queued values such as a minimum value. The cascaded queues are also successively sub-sampled to reduce the computing resources required to characterize the communications channel. The estimated metrics resulting from the above-described process may be used to adjust the data encoding process and increase data throughput on the communications channel.Type: ApplicationFiled: May 27, 2004Publication date: December 1, 2005Applicant: LSI LOGIC CORPORATIONInventor: Nagendra Goel
-
Patent number: 6969651Abstract: Nanotube memory cells are formed on a semiconductor substrate. Lower and upper memory cell chambers are formed by forming a first trench overlying the first and second contacts in a nitride layer, forming a second trench overlying the first and second contacts in a dielectric layer, depositing a nitride layer on the combined lower and upper chambers, and patterning the nitride layer to form an access hole to the nanotube layer and a second access hole to the second contact. A conductive layer is then deposited and patterned to form a top electrode contact and a nanotube layer contact. The conductive material closes the aperture created by the access hole.Type: GrantFiled: March 26, 2004Date of Patent: November 29, 2005Assignee: LSI Logic CorporationInventors: Hongqiang Lu, William Barth, Peter A. Burke
-
Patent number: 6969472Abstract: A method for manufacturing hemi-cylindrical and hemi-spherical micro structures is provided. A pattern is formed onto a substrate, and a layer of material is subsequently grown onto the substrate. Due to growth characteristics, the layer will form radially symmetric features when grown to an appropriate thickness.Type: GrantFiled: April 25, 2001Date of Patent: November 29, 2005Assignee: LSI Logic CorporationInventors: Dmitri V. Vezenov, John M. Guerra, Leonard Wan, Paul F. Sullivan
-
Patent number: 6970515Abstract: A line driver couples a data transceiver to a transmission line having a load impedance Z via a transformer with a turns ratio of 1:n, the data transceiver transmitting signals in a first frequency range and receiving signals in a second frequency range different from the first frequency range. The line driver includes an input port for receiving an input signal voltage, an output port for supplying an output signal voltage to the transformer, and a differential amplifier having a low pass filter for amplifying the input signal voltage and outputting an amplified signal voltage. The line driver further includes termination resistors having a resistance Rt, where R t = Z 2 ? n 2 × k ( 0 < k ? 1 ) , and a positive feedback path for coupling the output signal voltage from the output port to an appropriate node of the differential amplifier so that a synthesized output impedance substantially matches the load impedance Z over the second frequency range.Type: GrantFiled: June 8, 2001Date of Patent: November 29, 2005Assignee: LSI Logic CorporationInventors: Ara Bicakci, Cormac S. Conroy
-
Patent number: 6970516Abstract: A system generally having a first circuit, a second circuit, and a pair of non-crossing conductive paths. The first circuit may be configured to convert between (i) a serial signal on a first differential interface and (ii) a parallel signal. The pair of non-crossing conductive paths may connect the first differential interface with a second differential interface. The second circuit may be configured to invert the parallel signal in response to a control signal in an inverting state.Type: GrantFiled: August 29, 2001Date of Patent: November 29, 2005Assignee: LSI Logic CorporationInventors: Steven A. Schauer, Christopher D. Paulson
-
Patent number: 6969928Abstract: Disclosed is a system and method employing a magnetic proximity switch to enable the transfer of power between a power supply unit and a docking unit or to transfer data between a docking unit and a peripheral module such as a disk drive or controller module. Power may be transferred through the switch, or a signal from the switch may be employed to enable a control circuit. The control circuit may control a plurality of voltages or currents and may ramp voltages or currents to limit surge current when a module is installed or removed. The control unit may also be employed to place data and control signals in a high impedance state when a module is not docked, limiting electromagnetic radiation.Type: GrantFiled: May 31, 2002Date of Patent: November 29, 2005Assignee: LSI Logic CorporationInventor: George E. Hanson
-
Patent number: 6969621Abstract: Embodiments of the invention include an apparatus for uniformly contaminating samples. The apparatus includes a housing that contains a rotatable carousel for the holding samples. A drive element is used for rotating the carousel. The apparatus includes a contaminant dispenser for dispersing a contaminant onto the samples. The apparatus also includes a control element that can be used to control contaminant dose and carousel rotation rate and rotation time. A method for uniformly contaminating samples includes providing such a contamination chamber and placing a plurality of samples within the chamber. A contaminant is introduced into the chamber and the samples are spun so that the contaminant is uniformly distributed onto the spinning samples. After contamination the samples are removed from the chamber.Type: GrantFiled: December 9, 2002Date of Patent: November 29, 2005Assignee: LSI Logic CorporationInventor: Michael S. Gatov
-
Patent number: 6970208Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to present a first portion of an output data stream in response to a first portion of an input data stream. The second circuit may be configured to present a second portion of the output data stream in response to a second portion of the input data stream. The apparatus may be configured to perform color and gamma correction on the input data stream to generate the output data stream in response to one or more control signals. In one example, the apparatus may comprise block move engine (BME).Type: GrantFiled: September 21, 2001Date of Patent: November 29, 2005Assignee: LSI Logic CorporationInventors: David N. Pether, Ivan M. DiPrima
-
Patent number: 6969683Abstract: A method for forming a dual damascene interconnect in a dielectric layer is provided. Generally, a first aperture is etched in the dielectric. A poison barrier layer is formed over part of the dielectric, which prevents resist poisoning. A patterned mask is formed over the poison barrier layer. A second aperture is etched into the dielectric layer, wherein at least part of the first aperture shares the same area as at least part of the second aperture.Type: GrantFiled: December 31, 2003Date of Patent: November 29, 2005Assignee: LSI Logic CorporationInventors: Rongxiang Hu, Yongbae Kim, Sang-Yun Lee, Hiroaki Takikawa, Shumay Dou, Sarah Neuman, Philippe Schoenborn, Keith Chao, Dilip Vijay, Kai Zhang, Masaichi Eda
-
Patent number: 6971081Abstract: A substrate having a core with vias disposed therein. A reference layer is formed on the core, with voids in the reference layer that are formed around the vias in the core. Traces on a routing layer overlie the reference layer. Also included is a contact layer with contacts disposed in a contact pattern. The core is logically divided into sections, and the vias within a given one of the sections are aligned in rows substantially along a first direction. At least a portion of the vias are not aligned with the contact pattern. The voids in the reference layer within the given one of the sections are also aligned in rows substantially along the first direction and aligned with the vias. Further, the traces within the given one of each of the sections are also aligned substantially along the first direction between the rows of voids, and not substantially overlying the rows of voids.Type: GrantFiled: September 26, 2003Date of Patent: November 29, 2005Assignee: LSI Logic CorporationInventor: Arun Ramakrishnan
-
Patent number: 6970983Abstract: A multiple port system includes a plurality of port devices, each port device including a control register set, and a control bus coupled to the plurality of port devices. The control bus provides a control signal to each port device, and the control signal includes port address information and register address information. The control register set includes a set of registers responsive to the control signal if the port address information indicates the corresponding port device, and a designated register responsive to the control signal if the port address information indicates one of the plurality of the port devices and the register address information indicates the designated register.Type: GrantFiled: October 28, 2002Date of Patent: November 29, 2005Assignee: LSI Logic CorporationInventors: Shih-Hsing Huang, Narayanan Raman
-
Patent number: 6970622Abstract: An arrangement for controlling the transmission of a light signal is disclosed. The arrangement includes a first fiber optic line for transmitting the light signal and a light receiving unit operatively coupled to the first fiber optic line so that the light signal is received by the light receiving unit. The light receiving unit is operative to refract the light signal so that the light signal is substantially prevented from being transmitted through the light receiving unit if an intensity level of the light signal has a predetermined relationship with an intensity threshold level.Type: GrantFiled: July 19, 2001Date of Patent: November 29, 2005Assignee: LSI Logic CorporationInventor: Kunal N. Taravade
-
Publication number: 20050258881Abstract: A signal deskew circuit is provided, which includes first and second signal branches, each branch extending between a start location and a respective end location. Each signal branch includes a send path and a return path, which have substantially the same propagation delays. An adjustable delay buffer is coupled in the send and return paths of a first of the signal branches and has a delay, which is adjustable based on a respective adjust signal. A skew sensor coupled to the return paths of the first and second signal branches, which generates the respective adjust signal for the adjustable delay buffer based on a phase difference between signals on the return paths of the first and second signal branches.Type: ApplicationFiled: May 19, 2004Publication date: November 24, 2005Applicant: LSI Logic CorporationInventor: Richard Schultz
-
Patent number: RE38900Abstract: Automated photolithography of integrated circuit wafers is enabled with a processor connected to a Rayleigh derator, a form factor generator, a logic synthesizer, a layout generator, a lithography module and a wafer process. The Rayleigh derator receives manufacturing information resulting from yield data in the wafer process, and this manufacturing data is then used to derate the theoretical minimum feature size available for etching wafer masks given a known light source and object lens numerical aperture. This minimum feature size is then used by a form factor generator in sizing transistors in a net list to their smallest manufacturable size. A logic synthesizer then converts the net list into a physical design using a layout generator combined with user defined constraints. This physical design is then used by the mask lithography module to generate wafer masks for use in the semiconductor manufacturing.Type: GrantFiled: March 19, 1999Date of Patent: November 29, 2005Assignee: LSI Logic CorporationInventors: Michael D. Rostoker, Nicholas F. Pasch, Ashok K. Kapoor