Abstract: A method and system for designing a dummy grid in an open area of a circuit adjacent to at least one metal line comprising the circuits is disclosed. The method and system include patterning dummy lines in the dummy grid adjacent to metal signal lines, and patterning non-floating dummy lines in the dummy grid adjacent to metal power lines. The method and system further include varying sizes and spacing of the dummy lines in the respective columns of the dummy grid based on the distance between each column and the adjacent metal line, to achieve a balance between planarization and performance.

Abstract: Systems and methods for generating, maintaining, and using merged partitions to process requests of one or more host systems to storage partitions of one or more storage elements. Each merged partition maps to one or more storage partitions defined within one or more of the storage elements. The storage elements may be combined to form a storage complex. Each storage element of the storage complex may include one or more storage volumes, such as an array of storage volumes. A system includes a map processor and an interface controller. The map processor is configured for mapping the storage partitions of each storage element to generate one or more merged partitions. The interface controller is communicatively connected to the host systems and to the map processor for processing the requests of the host systems to the storage volumes based on the merged partitions.

Abstract: A system and method for communicating an image to a removable media device includes communicating the image from an image capture device to the removable media device over a wireless connection. The communicated image is stored in memory on the removable media device, and the stored image is deciphered. The deciphered image is recorded on removable media, the recorded image capable of being accessed on removable media device. In an additional aspect of the present invention, a method for communicating and formatting an image from an image capture device includes initiating a connection between an image capture device and an image storage device and querying the image storage device for a supported format. If the supported format differs from an image format, the image is deciphered to the supported format and communicated from the image capture device to the image storage device.

Abstract: Cells are placed into an integrated circuit floorplan by creating clusters of cells in modules, each cluster being composed of cells in a path connected to at least one flip-flop in the module, or of cells that are not in a path connected to any flip-flop. Regions are defined in the floorplan for placement of modules, and the clusters are placed into optimal locations in modules and placing the modules into optimal locations in the regions. T coordinates for the wires, modules and clusters are selectively recalculated. The clusters are moved in the floorplan for more uniform density, and the modules are assigned to regions based on module coordinates.

Abstract: A plurality of user-defined memories are mapped to pre-defined basic memories, such as defined on a base platform. The user-defined memories are dividing into classes of similar memories. A mapping technique is selected for members of a selected class of user-defined memories that minimizes the ratio (maxi,j(USEDi,j/AVAILi,j)) of basic memories that have been mapped to basic memories that are available for mapping. If the number of different memory mappings is smaller than a threshold the mapping technique is applied to each user-defined memory. If the number of different memory mappings is greater than the threshold, the groups are arranged in ordered queues of single memory types based on a mapping price and the mapping technique is selected based on a memory of each group and is applied to each user-defined memory in the respective group.

Abstract: A set of tools is provided herein that produces useful, proven, and correct integrated semiconductor chips. Having as input either a customer's requirements for a chip, or a design specification for a partially manufactured semiconductor chip, the tools generate the RTL for control plane interconnect; memory composition, test, and manufacture; embedded logic analysis, trace interconnection, and utilization of spare resources on the chip; I/O qualification, JTAG, boundary scan, and SSO analysis; testable clock generation, control, and distribution; interconnection of all of the shared logic in a testable manner from a transistor fabric and/or configurable blocks in the slice. The input customer requirements are first conditioned by RTL analysis tools to quickly implement its logic. The slice definition and the RTL shell provides the correct logic for a set of logic interfaces for the design specification to connect. The tools share a common database so that logical interactions do not require multiple entries.

Abstract: Disclosed is a method for continuing a rebuilding process of a RAID system by flagging a block of data as being bad when a media error or other error occurs that prohibits the reconstruction of data. The block of data may be flagged by writing a bad error correction code to the block of data, by keeping a log of bad blocks of data, or by otherwise indicating that the block of data is known bad.

Abstract: A register address generation tool is used during the design of semiconductor products. For those registers and/or memories that are addressable on a bus, the register address generation tool creates the interconnect RTL, header files, static timing analysis constraint files, and verification testcases. The tool also maintains coherence between what has been generated and the available resources for the design of the semiconductor product in a design. If there are any registers and/or memories that are not being used, the register address generation tool may further generate the RTL that will convert these unused resources to performance-enhancing features such as control registers, status registers, etc. The register address generation tool read a design database having an application set to determine what hardmacs and what transistor fabric is available. It also receives as input a bus specification and address parameters.

Abstract: An apparatus comprising a media access controller (MAC), a configurable packet switch, and a network protocol stack in silicon. The network protocol stack may be configured to couple the media access controller to the configurable packet switch.

Abstract: Methods and systems are provided for thermal self-monitoring of integrated circuits. Temperature is sensed, digitized, encoded, and compared to one or more threshold values by circuits added within an integrated circuit. A signal produced by a thermal diode within an integrated circuit is applied to an analog to digital converter and may be compared to one or more threshold values to produce a digital over temperature condition signal. An appropriate cooling action may be initiated by processing of the digital signal so produced. Also provided are methods and systems to alter the range and resolution of the temperature threshold comparisons.

Abstract: A region on a substrate contains multiple transistors in parallel that share a single salicided polysilicon gate electrode. Above or below the gate electrode are formed multiple plugs of refractory material along the length of the gate electrode. The multiple plugs of refractory material electrically interconnect the gate signal line and the salicided polysilicon gate electrode. The plug material is selected to minimize the work function between it and the salicided polysilicon gate electrode.

Abstract: The present invention is an integrated circuit containing multiple digital signal processors (DSPs). A single host processor interface is also placed on the chip to connect the multiple DSPs to the host. A separate direct memory access (DMA) unit is provided for each DSP to facilitate flow of data to and from a data memory for each DSP. Each DSP also includes an instruction memory.

Abstract: A footprint based optimal characterization of intellectual property (IP) for more deterministic physical integration. The physical integration characteristics are based upon IP physical integration at an anchor point in a pre-defined IC platform. IP footprint characteristics are identified as fixed, variable or prioritized to each other, and bounding constraints are defined based on a set of characteristics for the IP, the platform characteristics and IC design requirements. The IP is physically synthesized using the bounding constraints. The synthesized IP is tested and the bounding constraints are iteratively modified until the characteristics of the synthesized IP are optimized/captured.

Abstract: Disclosed is a method and apparatus for providing a universal SCSI bus interface in which bus performance is not degraded, and the analyzer is not negatively influenced by post processing while maintaining the ability to filter and store data using any of a number of generic logic analyzers. The SCSI bus interface does not rely on a specific clock speed and maintains the ability to view both raw data and protocol errors. The universal SCSI bus interface embodiments described herein produce stable clock signals for use by an analyzer in a form that is phase and frequency stabilized with the SCSI bus clock. This allows data sampling to mimic the performance characteristics of a device attached to the SCSI bus thereby minimizing sampling error.

Abstract: The present invention is directed to a configurable input/output interface and method for data transfer between a host and a target in a network environment. A method for providing data transfer between a host and a target in a network environment by a configurable input/output interface includes providing a logical identifier. The logical identifier is configurable for operation in at least two modes, the at least two modes including at least two of referencing multiple data transfer routes between the target and the input/output device utilizing a single logical identifier, referencing a single route between the target and the input/output device utilizing a logical identifier, and referencing a physical address of the target utilizing a logical identifier. Communications between the host and the target are managed by selecting a mode of the at least two modes operable by the input/output interface.

Abstract: A carbon nanotube memory cell for an integrated circuit wherein a chamber is constructed in a layer of a dielectric material such as silicon nitride down to a first electrical contact. This chamber is filled with polysilicon. A layer of a carbon nanotube mat or ribbon is formed over the silicon nitride layer and the chamber. A dielectric material, such as an oxide layer, is formed over the nanotube strips and patterned to form an upper chamber down to the ribbon layer to permit the ribbon to move into the upper chamber or into the lower chamber. The upper chamber is then filled with polysilicon. A silicon nitride layer is formed over the oxide layer and a contact opening is formed down to the ribbon and filled with tungsten that is then patterned to form metal lines. Any exposed silicon nitride is removed. A polysilicon layer is formed over the tungsten lines and anisotropically etched to remove polysilicon on the horizontal surfaces but leave polysilicon sidewall spacers.

Abstract: In some embodiments, a system includes a memory device in a first clock domain region and a memory device and a digital signal processing (DSP) sub-system in a second clock domain region. In addition, a plurality of asynchronous first-in first-out (FIFO) data structures, each comprising a read interface, a write interface, and one or more data slots, store data generated from the DSP sub-system. The read interface operates in the first clock domain, and the write interface operates in the second clock domain.

Abstract: A macro cell is provided for an integrated circuit design having an input-output (IO) region with a plurality of IO buffer cells physically dispersed with other cells in IO slots along an interface portion of the IO region. The macro cell includes a plurality of macro cell IO signal slots that are physically dispersed so as to substantially align with the IO buffer cells in the interface portion. The macro cell also includes an interface definition having a plurality of interface IO signal nets, which are routed to corresponding ones of the plurality of macro cell signal slots. The macro cell is adapted to be instantiated as a unit in the integrated circuit design.

Abstract: A method for structuring hardware description language code characterizes a peripheral design so as to facilitate multiple use of the code with different peripheral design configurations in a chip. The code provides one or more configuration options for the peripheral design in a configuration section of the hardware description language code. The one or more configuration options are differentiated by a configuration variable. The configuration options are selected by initializing a selected peripheral design configuration with the configuration variable, such that the value of the configuration variable determines the selection for that specific instance.

Abstract: A transparent switch is able to emulate the arbitration and addressing steps for devices that are normally connected to a bus-type communications network. The switch is connected to the devices in a star-type arrangement, with each device connected to a separate port. The switch performs the arbitration and addressing communications with a transmitting device, selects the proper port as defined by the addressing communication, arbitrates with the receiving device, and then switches the communications to occur directly from the transmitting device to the receiving device.