Abstract: A dual purpose PCI-X DDR configurable terminator/driver providing programmable termination of the interface in a PCI-X system a plurality of N-channel devices divided into at least two groups and a plurality of P-channel devices also divided into at least two groups. A driver control individually controls selected ones of the groups of N-channel and P-channel devices on or off for providing internal termination to the transmission line. The configurable PCI-X DDR driver/terminator is configurable in three termination modes: pull-up mode, pull-down mode, and symmetric mode.

Abstract: A host computer environment includes a driver stack having a disk driver and a host bus adapter (HBA) driver. The driver stack further includes a multipath driver functionally embedded between the disk driver and HBA driver. At this hierarchical layer of the driver stack, the multipath driver functions at the command transport protocol level. The disk driver effectively views the multipath driver as a HBA driver type, while the HBA driver effectively views the multipath driver as a disk driver type. The multipath driver is configured to instantiate proxy virtual paths to the disk array that are visible to the host operating system but otherwise conceal the underlying physical paths. The multipath driver retains knowledge of the mapping between the physical and virtual paths. The disk array is configured to report itself to the OS as a non-disk device type, although its true identity is known by the multipath driver.

Abstract: A digital multi-phase clock generator includes a reference clock input and first and second digitally-programmable delay lines. The first and second delay lines are coupled in parallel with one another, in series with the reference clock input. Each delay line includes a delay control input. The first delay line has a plurality of phase outputs which are synchronized with the reference clock input and have different phases from one another. The generator further includes a phase detector and a delay control circuit, which are coupled with second delay line to form a phase-locked loop. The delay control circuit has a digital delay control output, which is coupled to the delay control inputs of both the first and second delay lines. The phase-locked loop adjusts delay through the first and second delay lines to lock a phase of an output of the second delay line to a phase of the reference clock input.

Abstract: An apparatus comprising a first circuit, a second circuit and a third circuit. The first circuit may be configured to generate an upconverted signal in response to an input signal and a first oscillation signal. The second circuit may be configured to generate a downconverted signal in response to the upconverted signal and as second oscillation signal. The third circuit may be configured to generate an output signal in response to the downconverted signal and a third oscillation signal derived from the second oscillation signal. The upconverting and downconverting may filter undesired channels from the output signal.

Abstract: A novel device which efficiently decodes data encoded with a cyclic code in communications systems where a convolutional code is applied after the cyclic code during encoding. Specifically, the device accepts data provided in time reversed order by a Viterbi decoder which decodes the convolutional code. In a preferred version, the device employs linear feedback shift registers with multiple feedback paths. A set of multipliers corresponding to a set of coefficients is interposed in the feedback paths such that when data is shifted through the feedback shift registers, the device performs division by x for an input bit equal to 0, and, for an input bit equal to 1, performs division by x and then adds xk+m?1. The set of multipliers includes a set of weighting multipliers corresponding to coefficients of a weighting polynomial such that addition of xk+m?1 is performed for an input bit equal to 1.

Abstract: Systems and methods for controlling a display device include receiving a source video signal from a video source; storing video pixels in one or more line buffers; enhancing the video signal on the fly using data stored in the line buffers; if image enhancement is not necessary, rendering the source video signal and otherwise rendering the enhanced video signal.

Abstract: An apparatus, system, and method are disclosed for reducing integrated circuit peeling. This invention reduces integrated circuit peeling by providing a wafer with a solventphilic layer and removing unwanted film using a solvent that is philic to the solventphilic layer. In one embodiment, a boundary is provided to reduce the rotation speed precision required to reach the desired etching distance. In certain embodiments, a wet edge etching process is used to remove unwanted film from the perimeter of the solventphilic layer. In certain embodiments, the solventphilic layer comprises a hydrophilic layer such as silicon nitride, and the solvent comprises a solution of water and hydrogen fluoride.

Abstract: A layered test pattern for measuring registration and critical dimension (CD) for multi-layer semiconductor integrated circuits is disclosed. A first layer includes a first pattern having vertical and horizontal portions. A second layer is formed over the first layer and includes a second pattern having vertical and horizontal portions having nominal vertical and horizontal phase shifts with respect to the vertical and horizontal portions, respectively, of the first pattern. The vertical and horizontal portions include periodically repeating vertical lines and horizontal lines, respectively. The nominal phase shifts may be half of the period of the vertical and horizontal lines. A scatterometry tool measures the width of the lines and the phase shift of the first pattern relative to the second pattern. The width of the lines corresponds to CD, whereas the difference between the measured phase shift and the nominal phase shift indicates variation in registration.

Abstract: Techniques for vaporizing and handling a vaporized metallic element or metallic element salt with a heated inert carrier gas for further processing. The vaporized metallic element or salt is carried by an inert carrier gas heated to the same temperature as the vaporizing temperature to a heated processing chamber. The metal or salt vapor may be ionized (and implanted) or deposited on substrates. Apparatus for accomplishing these techniques, which include carrier gas heating chambers and heated processing chambers are also provided.

Abstract: For use in a processor having an external memory interface, an instruction prefetch mechanism, a method of prefetching instructions and a digital signal processor incorporating the mechanism or the method. In one embodiment, the mechanism includes: (1) a branch predictor that predicts whether a branch is to be taken, (2) prefetch circuitry, coupled to the branch predictor, that prefetches instructions associated with the branch via the external memory interface if the branch is taken and prefetches sequential instructions via the external memory interface if the branch is not taken and (3) a loop recognizer, coupled to the prefetch circuitry, that determines whether a loop is present in fetched instructions and reinstates a validity of instructions in the loop and prevents the prefetch circuitry from prefetching instructions outside of the loop until the loop completes execution.

Abstract: A system and method for testing the signals on a parallel communication bus uses a single printed circuit board that connects to the bus. The signals from the bus may be passively and actively filtered prior to a multiplexer. The multiplexer may be controlled by a variety of inputs, including communications over a second bus by a remote device. The output of the multiplexer is one or more probe points that may be connected to a measurement device.

Abstract: A method and computer program are disclosed for optimizing RTL code for an integrated circuit design that include steps of: (a) receiving as input a first register transfer level code for an integrated circuit design; (b) receiving as input a user defined optimum multiplex structure; (c) analyzing the first register transfer level code to identify a critical multiplex structure; (d) partitioning the global multiplex structure into local multiplex structures each identical to the user defined optimum multiplex structure; and (e) generating as output a second register transfer level code for the integrated circuit design that replaces the global multiplex structure with the local multiplex structures.

Abstract: Methods and systems for managing control structure access by a processor are disclosed. In general, a processor can communicate with a plurality of control structures. A memory window manager can then be implemented, which communicates with said processor and said plurality of control structures. The memory window manager specifies which control structure among said plurality of control structures is accessible by said processor. The memory window manager also specifies which control structure can be mapped into an address space of said processor.

Abstract: Methods and associated structures for transparently mapping SCSI2 reservation protocol exchanges into corresponding SCSI3 reservation protocol exchanges. A mapping element may be operable within host systems that support SCSI2 reservation protocols. The mapping element intercepts and translates SCSI2 reservation exchanges into corresponding SCSI3 reservation protocol exchanges. The mapped exchanges may then be forwarded to a SCSI3 based storage subsystem to permit such an updated storage subsystem to appropriately interact with a cluster of host systems. The cluster of host systems may then be comprised of a heterogeneous mix of SCSI2 and SCSI3 based host applications.

Abstract: An automatic gain control system combining both analog and digital gain units, both controlled by a common digital control system. The overall system gain settings are selected by a combination of analog gain settings and digital gain settings. The number of analog gain settings is less than the total number of system gain settings, so that the board or chip area required for the analog gain settings is reduced, while sufficient range is provided to maintain a good signal to noise ratio from an A/D converter. When a required gain adjustment exceeds one step of the analog gain stage, the system simultaneously adjusts the analog gain and the digital gain unit to provide a smooth transition.

Abstract: An apparatus comprising a first transistor pair, second transistor pair, a third transistor pair and a fourth transistor pair. The first transistor pair may be (i) implemented as thin oxide devices and (ii) configured to receive a differential input signal. The second transistor pair may be (i) implemented as thick oxide devices and (ii) configured to generate a differential output signal in response to the differential input signal. The output signal has a voltage higher than the input signal. The third transistor pair may be (i) connected between the first and second transistor pairs and (ii) configured to protect the first transistor pair. The fourth transistor pair may be (i) connected between the third transistor pair and a ground and (ii) configured to increase an operating speed of the apparatus.

Abstract: A circuit for measuring the performance of a memory cell. The circuit includes a ring oscillator, which includes a plurality of memory cells. The performance of the memory cell can be determined from an oscillation frequency of the ring oscillator. The circuit accurately verifies the performance of the memory cell without modifying the memory cell. This avoids altering the transient AC characteristics of the memory cell when predicting its performance.

Abstract: A built in self test circuit for testing an analog to digital converter. An up counter receives a test input and a first clock signal and provides and upper limit. A down counter receives the test input and the first clock signal, and provides a lower limit. A digital to analog converter receives the test input and a second clock signal, and provides an analog output. Circuitry provides the analog output and a third clock signal to the analog to digital converter, and the analog to digital converter thereby produces a digital signal. An upper limit comparator receives the upper limit and the digital signal, and provides an upper limit status signal indicating whether the digital signal violates the upper limit. A lower limit comparator receives the lower limit and the digital signal, and provides a lower limit status signal indicating whether the digital signal violates the lower limit.

Abstract: A self-sealing apparatus for containing electrical energy associated with electrical components. The apparatus includes one or more removable devices maintained by a housing. Each of the removable devices contains electrical components therein and is separated from at least one other removable device by a clearance gap formed therebetween. A self-sealing barrier can be formed from the clearance gap, wherein the clearance gap surrounds the removable device in order to contain electrical energy associated with the electrical components when the electrical components are maintained within the removable device or extracted or inserted from or into the removable device.

Abstract: Disclosed is a method of analyzing an integrated-circuit system that is accurate for high frequency analysis and can predict problems at high frequencies that do not occur when the circuit is used at lower frequencies.