Abstract: A disclosed coprocessor receives a user-defined command during execution of an instruction including the user-defined command, and performs a predetermined function in response to the user-defined command. The user-defined command includes multiple ordered bits having values assigned by a user. In one embodiment, the coprocessor includes logic coupled to receive the user-defined command and a datapath. The logic produces a control value in response to the user-defined command. The datapath receives data and the control value, and performs the predetermined function dependent upon the control value. In one embodiment, the predetermined function is a motion estimation function. Data processing systems are described including a processor coupled to the coprocessor. Another disclosed data processing system includes an arbiter coupled between a processor and multiple coprocessors.

Abstract: The present invention is directed to a system and method of cache management for storage controllers. In an aspect of the present invention, a system for storing electronic data may include a host and a data storage apparatus communicatively coupled to the host. The host has cache coherency functionality. The data storage apparatus includes a first storage controller communicatively coupled to at least one storage device, the first storage controller further coupled to a first cache. A second storage controller is also included, which is communicatively coupled to at least one storage device, the second storage controller further coupled to a second cache. The cache coherency functionality of the host provides coherency of the first cache coupled to the first storage controller with the second cache coupled to the second storage controller.

Abstract: A system, method and apparatus for providing and utilizing a storage cache descriptor by a storage controller are disclosed which provide the ability to effectively balance the size of storage controller cache blocks and the amount of data transferred in anticipation of requests, such as requests by a host. The apparatus may include a storage device, a storage controller and a cache. The storage controller stores electronic data in the cache by including a cache descriptor that defines data contained in a cache block, the cache descriptor including at least one field describing a device block of the cache block. The at least one field may include, by way of example, at least one of a present field, modified field, pinned field and write-in progress field.

Abstract: The present invention is directed to a method and system for providing, a host input/output (I/O) module, a controller and application specific integrated circuit (ASIC) for utilization in transparent switched fabric data storage transport. The system implements I/O modules capable of translating between communication protocols for providing common message passing multi-channel data transport for data storage while providing apparent I/O circuit exclusivity to controllers. Implementing the system of the present invention allows for a common data transport system permitting component scalability and virtualization.

Abstract: A method includes steps of: (a) providing a wafer on which a film has been deposited; (b) exposing an annular area in an edge exclusion zone of the wafer to radiation having a wavelength suitable for patterning the film in the annular area; and (c) modulating the radiation while exposing the annular area to form a pattern in the film in the annular area.

Abstract: The present invention is a computer-based system for managing projects. It allows the user to input data concerning a project and associate individuals with the project. The system then determines a deadline for completing a task associated with the project and send out reminders accordingly. The system provides the user a number of options not available on the conventional docketing systems, such as automatically increasing the frequency with which reminders are sent as the deadline approaches, and automatically increasing the number of individuals to whom the reminders are sent as the deadline draws near.

Abstract: A method of accurately estimating horizontal and vertical wire densities in a datapath or hardmac. The method provides that the datapath or hardmac is divided into areas, and mathematical expectations are calculated for full and partial horizontal and vertical segments for each of the areas. The mathematical expectations are summed for both the horizontal and vertical segments, and this is done for each connection within the datapath or hardmac in order to estimate both horizontal and vertical wire densities. A congestion map can be created, and 100% detail routing is effectively guaranteed as a result of using the method. Preferably, a model with minimum bends is used in areas with low wire density, and models with more bends are used in areas with middle and high wire density.

Abstract: The present invention provides a system for implementing a configurable integrated circuit (IC). Aspects of the invention include an IC die; a plurality of input/outputs (I/Os) coupled to the IC die; and a plurality power planes coupled to the IC die for providing power to the plurality of I/Os at different voltages. The plurality of power planes are configured concentrically around the IC die so that any one or more of the I/Os at any location on the IC die can be individually configured to connect to any of the power planes. As a result, any number of I/Os available on the IC die can operate at a given voltage.

Abstract: A method for decoding using a general purpose processor, comprising the steps of extracting a bit field from a data stream; extracting one or more properties from the data stream; matching the one or more properties with one or more tags in a content addressable memory; and generating a new address in response to the content addressable memory.

Abstract: An inductor-capacitor voltage controlled oscillator is implemented using an active inductor. The active inductor may use bipolar technology or CMOS technology. The VCO with an active inductor offers a more compact design and is useable with flip chip technology. The active inductor may be implemented in bipolar junction or complementary metal oxide semiconductor technology. The configuration of the voltage controlled oscillator with an active inductor of the present invention is fully differential and fully symmetric.

Abstract: A method for generating a modified view of a circuit layout. In a first step, the method includes receiving the circuit layout from a design rule clean database. In a second step, the method includes extracting a base wafer layout from the circuit layout according to a set of computer executable instructions. In a third step, the method includes modifying the base wafer layout according to the set of computer executable instructions.

Abstract: A method for testing semiconductor devices advantageously increases manufacturing yields. The method includes generating memory repair data for a wafer die by writing at least one predetermined digital bit pattern into a memory on the wafer die, reading the at least one predetermined digital bit pattern back out of the memory, comparing the at least one predetermined digital bit pattern read out from the memory against the at least one predetermined digital bit pattern written into the memory, and storing results of the comparison as the memory repair data. The writing and reading are performed a plurality of times, each time with a different voltage and clock frequency combination being applied to the wafer die. The memory repair data is programmed into the wafer die, and the wafer die is assembled into a packaged semiconductor device.

Abstract: The present invention is directed to a method and apparatus for mapping platform-based design to multiple foundry processes. According to an exemplary aspect of the present invention, a method for mapping platform-based design to multiple foundry processes may include the following steps. First, a virtual process is defined to include at least one fabrication process. A virtual process is a totality of variables associated with the population of candidate processes and any other process of interest, which might be purely hypothetical, that would be capable, in principle, of accommodating some or all slices. A virtual process may or may not be realized and is an abstract logical container for a population of processes. Then, the virtual process may be stored into a database. The virtual process may be in a representation including a list of attributes of entities making up the fabrication process. Next, optimization of the database may be performed using mathematical and statistical tools.

Abstract: An innovative circuit is disclosed that enhances performance on a SCSI bus by pipelining nexuses in order to associate all nexus attributes on a per nexus basis. For example, a pipeline of nexuses is created so as to associate all of the nexus attributes from different connections involved. A plurality of load stages is provided whereby each load stage can latch all nexus attributes received at that stage. The latched nexus attributes can be loaded and stored at that stage or shifted to the next stage. As a result of the loading and shifting operations, a pipeline of nexuses is created that associates all of the nexus attributes received from the different connections on a per nexus basis. Therefore, all types of data traffic can be processed concurrently on a SCSI bus, which enhances data throughput and bus performance.

Abstract: The present invention provides a diffusion resistor that is formed in the substrate. A diffusion region is formed within the substrate that contains a first and second contact region. These contact regions extend downward from the surface of the substrate. A third contact is located within the diffusion region between the first and second contacts. This contact also extends downward from the surface of the substrate. These contacts are connected to metal layers. The first and second contacts form the two ends of the diffusion resistor. The third contact forms a Schottky diode such that application of a voltage to this contact forms a depletion region within the diffusion region. The depletion region changes in size depending on the voltage applied to the third contact to change the resistance of the depletion resistor.

Abstract: The present invention discloses a motion estimation method for MPEG video sequences. The method makes use of a global motion estimation algorithm to determine a set of dominant motion components. A simultaneous Full Search Block Matching (FSBM) search is conducted utilizing each dominant component for every block in a current frame. The results of each FSBM search are then compared to determine the best motion vector.

Abstract: A method of testing integrated circuits. Each of the integrated circuits is tested with a first test at a first level of testing at a preceding testing step in a fabrication cycle of the integrated circuits to produce first test results associated with a first characteristic of the integrated circuits. The first test results are recorded with associated integrated circuit identification information. The integrated circuits are logically subdivided into bins based at least in part on the associated integrated circuit identification information. A defectivity value is calculated for each bin of subdivided integrated circuits based at least in part on the first test results recorded with the associated integrated circuit identification information.

Abstract: An apparatus comprising a first control circuit, a second control circuit, a latch circuit and a flip-flop. The first control circuit may be configured to generate a first control signal in response to (i) an input signal from a fuse and (ii) one or more read signals. The latch circuit may be configured to change status in response to the first control signal. The second control circuit may be configured to change the state of the latch circuit in response to (i) one or more read signals and (ii) one or more set signals. The flip-flop may be configured to capture the state of the fuse in response to changing the state of the latch circuit with the first control circuit or the second control circuit.

Abstract: Apparatus and process identifies a maximum or minimum value among a plurality of binary values on a plurality of a-bit wide wires in an integrated circuit module. An N-bit vector K is calculated based on n most significant bits of all a-bit binary signals, where N=2n. M N-bit vectors K—0, . . . ,K_(M?1) are calculated based on the n most significant and the m least significant bits of all a-bit binary signals, where M is at least 2m?1. A table is constructed from vectors K—0, . . . ,K(M?1) to create table vectors. A table vector is selected based on vector K, is used to derive a vector P, which in turn is used to select another table vector. The minimum or maximum binary value is identified from the two selected table vectors.

Abstract: A process for removal of a photoresist mask used to etch openings in low k carbon-doped silicon oxide dielectric material of an integrated circuit structure, and for removing etch residues remaining from either the etching of the openings or removal of the resist mask, while inhibiting damage to the low k dielectric material comprises. The structure is exposed to a reducing plasma to remove a portion of the photoresist mask, and to remove a portion of the residues remaining from formation of the openings in the layer of low k dielectric material. The structure is then exposed to an oxidizing plasma to remove any remaining etch residues from the openings in the layer of low k dielectric material or removal of the resist mask.