Abstract: A clock generating circuit for a pseudo dual port memory incorporates feedback, delays, and latches to ensure that the write (read) operation clock pulse is sufficiently spaced in time from the read (write) operation clock. The clock generating circuit receives an external clock, a read enable signal, a write enable signal, and a reset signal as inputs. Advantages include minimization of the clock cycle time and operation unaffected by the duty ratio of an external clock. Delay circuitry may be added such that the generated clock signal has sufficient fan out and is sufficiently stable.

Abstract: Methods and associated structure for providing broadcast of PCI bus transactions using device ID messaging (DIM) features of the PCI bus specifications. A vendor defined class of messages are defined using device ID messaging to provide broadcast of messages across PCI bus bridge devices to multiple PCI bus segments. One aspect hereof provides for using implicitly addressed device ID messaging such that bridge devices, compatible with the vendor defined message classes, will forward the message upstream and downstream. Another feature provides for use of explicitly addressed device ID messaging to effectuate the desired broadcast. Another aspect hereof provides for translation of a received DIM formatted message with broadcast information and applying the broadcast information to a second bus segment as a standard PCI broadcast transaction.

Abstract: A method for generating a plurality of timing constraints for a circuit design is disclosed. The method generally includes the steps of (A) identifying a plurality of clock signals by analyzing the circuit design, (B) determining a plurality of relationships among the clock signals and (C) generating the timing constraints for the circuit design in response to the clock signals and the relationships.

Abstract: A logical gate and a comparator are used to detect page boundaries in a data stream. A current address and a predetermined page size, that is an integer power of 2, are compared using a Boolean logic gate such as AND or XOR to detect a page boundary in a data stream. The output from the Boolean logic gate is compared to a predetermined value to cause a signal to be generated, indicating the end of the page.

Abstract: For use in a floating-point unit that supports floating-point formats having fractional parts of varying widths and employs a datapath wider than the fractional parts, a circuit and method for normalizing and rounding floating-point results and processor incorporating the circuit or the method. In one embodiment, the circuit includes: (1) left-shift circuitry for aligning a fractional part of the floating-point result with a most significant bit of the datapath and irrespective of a width of the fractional part to yield a shifted fractional part and (2) rounding circuitry, coupled to the shift circuitry, that rounds the shifted fractional part.

Abstract: A method for determining outlier data points in. A subset of dataset patterns is selected from a set of mathematical dataset patterns, and the subset of dataset patterns is combined into a composite dataset. The composite dataset is compared to the dataset, and a degree of correlation between the composite dataset and the dataset is determined. Data points within the composite dataset are selectively weighted to improve the degree of correlation, and the steps described above are selectively iteratively repeated until the degree of correlation is at least a desired value. Residuals for the data points within the composite dataset are selectively determined. At least one of the weighted data points within the composite dataset that are weighted within a first specified range, and data points within the composite dataset that have a residual within a second specified range, are selectively output as outlier data points.

Abstract: The present invention may provide a circuit generally having a plurality of addressable memory cells and an access control circuit. The access control circuit may be configured to intercept an access to a faulty cell of the plurality of addressable memory cells. The access control circuit may be further configured to redirect the access to a spare cell of the plurality of addressable memory cells.

Abstract: A routing structure for a transceiver core, the routing structure including a transmitter block design and a receiver block design. The transmitter block design includes two dedicated transmitter power contacts, two common ground contacts, and two transmitter signal contacts in a transmitter differential pair. The two transmitter signal contacts are both adjacent each of the two dedicated transmitter power contacts and each of the two common ground contacts. The receiver block design includes two dedicated receiver power contacts, two common ground contacts, and two receiver signal contacts in a receiver differential pair. The two receiver signal contacts are both adjacent each of the two dedicated receiver power contacts and each of the two common ground contacts.

Abstract: The present invention is directed to a method for generating a tech-library for a logic function. A logic function has many representations. For each representation, a circuit for realizing the representation is decomposed into a combination of instances. An instance is a component logic circuit of a general logic circuit. There are pre-created tech-libraries for the instances. For example, a pre-created tech-library is created by categorizing tech-descriptions for primitive physical circuits based on a negation index. Thus, tech-descriptions for a circuit for realizing a representation are calculated from a combination of elements of the pre-created tech-libraries. Each calculated tech-description is compared with each existing element of a tech-library for the logic function. When a calculated tech-description has at least one marked parameter better or smaller than that of all existing elements of the tech-library for the logic function, the calculated tech-description is added to the tech-library.

Abstract: An apparatus comprising a first circuit, a second circuit and an output circuit. The first circuit may be configured to generate (i) one of a first set of entropy coded input signals or a second set of entropy coded input signals and (ii) a data path signal. The second circuit may be configured to generate (i) a first set of entropy encoded output signals in response to decoding the second set of entropy coded input signals, or (ii) a second set of entropy coded output signals in response to decoding the first set of entropy coded input signals. The second circuit may provide real time decoding and encoding on a macroblock basis. The output circuit may be configured to present an output signal in response to (i) one of the first set of entropy coded output signals or the second set of entropy coded output signals and (ii) the data path signal.

Abstract: A method for re-using diffused cell-based IP blocks in a structured application specific integrated circuit comprising the steps of (A) implementing one or more blocks of intellectual property (IP) using a plurality of cell-based building blocks and (B) providing one or more alternative views for at least one of the one or more blocks of intellectual property.

Abstract: Disclosed is a test method for a computer microprocessor adapted to stress the data transfer interfaces within a microprocessor. The method incorporates patterns designed to stress the interfaces and are further repeated in different widths such that interfaces of various bus widths are fully stressed. Further, the method begins with the various test patterns preloaded into memory to maximize the speed and thus the stress of the test.

Abstract: Circuitry and a method for testing oversampled Analog to Digital converters. The voltage reference is used as the input signal, thus eliminating the need for a special signal generator. The dynamic signal is obtained by not sampling the voltage reference on every sample. Instead, a state machine is used to gate the sampling of the voltage reference, which in turn causes a varying amount of change to be injected into the first integrator in the converter. As a result, the state machine effectively simulates many input levels.

Abstract: A system for layout of a module in an integrated circuit layout pattern has a cell library and a cell placement system. The cell library includes a plurality of cells. The cell placement system is adapted to select one or more cells from the cell library and to locally place each selected cell within the module layout so that each cell pin of the selected cells and each port of the module layout occupies a unique vertical routing track within the module layout.

Abstract: A method for calculating ramptime propagation for integrated circuit layout patterns having pins interconnected in an oriented graph in one or more closed loops is described. Ramptime values are calculated for a first set of the pins, which are not connected to a closed loop while leaving a second set of the pins with unknown ramptime values. One or more closed loops are identified by backtracking from the pins in the second set with unknown ramptime values. A ramptime value for each pin in the one or more closed loops is calculated iteratively.

Abstract: A simplified boundary scan test method capable of performing boundary test scanning of semiconductor chips. The test method comprises providing valid test data to a first terminal of the semiconductor device and purposely providing invalid test data to a second terminal of the semiconductor device in a predetermined pattern algorithm. Preload data is also preloaded onto the semiconductor device. The valid and invalid test data is then captured in the semiconductor device. If the captured data is as expected, it signifies that there is no problem with the boundary scan circuitry on the device. On the other hand if the captured data differs from what is expected, it signifies that there may be a problem with the boundary scan circuitry.

Abstract: The present disclosure is directed to ball assignment schemes for ball grid array packages in integrated circuits with increased signal count. The ball assignment scheme includes an array of electrical contacts. The array has a first diagonal including a pair of signal contacts adjacent to a pair of first-type voltage supply contacts. The array further includes a crossing diagonal having a pair of adjacent second-type voltage supply contacts, which crosses the first diagonal between the pair of signal contacts such that the pair of second-type voltage supply contacts oppose one another relative to the first diagonal.

Abstract: A system and method for designing a complex electronic circuit by simulating blocks of the circuit using various simulators to produce a net list, designing the physical layout of the circuit using a layout tool that produces a layout verses schematic reference file, mapping the reference file to the net list to create a mapping file, and analyzing the mapping file to verify that the layout meets various criteria. Each block may be verified using simulation tools that are appropriate for that piece of the overall circuit, and using conditions that may maximize the strain on the circuit. The results from the simulations are compared to the physical layout to determine if the physical layout is able to properly conduct the electrical signals.

Abstract: The design of integrated circuits, i.e., semiconductor products, is made easier with a semiconductor platform having versatile power mesh that is capable of supporting simultaneous operations having different frequencies on the semiconductor product; e.g., higher frequency operations may be embedded as diffused blocks within the lower layers or may be programmed from a configurable transistor fabric above the diffused layers. Preferably the power mesh is located above the layers having the operations requiring the different frequencies, and may be fixed in an application set given to a chip designer or may be configurable by the designer her/himself. For example, to support high speed communications adjacent an embedded high speed data transceiver, the transistor fabric may be programmed as a data link layer having higher performance requirements than the rest of the integrated circuit.

Abstract: A method of canceling noise in analog circuits is described along with noise cancellation circuits. Analog circuits are sensitive to noise. Especially in mixed signal environments where digital circuits and analog circuits are combined, the noise generated by relatively noisy digital circuits often cause the analog circuits to produce incorrect output signals. Instead of shielding or separating the susceptible analog circuits from noisy digital circuits, additional circuitry is added where one of the added circuits, denoted as the noise separator circuit, produce only the noise component of the output signal, the first output, of the analog circuit adversely affected by the noise. Then, another circuit is used to subtract the noise from the first output, thereby producing a noise-free output signal. Alternatively, the noise separator circuit can be made to produce the inverse of the first output, including the inverse of the noise.