Patents Assigned to LSI Logic
  • Method and apparatus of IC implementation based on C++ language description
    Patent number: 7082593
    Abstract: The present invention is directed to a method and apparatus of IC implementation based on a C++ language description. In an exemplary aspect of the present invention, a method for evaluating a C++ description by an IC includes the following steps. First, a C++ description including a C++ program is provided. Then, the C++ program is stored in a first memory module (e.g., a ROM, or the like) of an IC. Next, a scalar input and/or an input array may be provided to the IC. Then, the C++ program may be executed by a control device module of the IC. Next, a scalar output and/or an output array may be read from the IC.
    Type: Grant
    Filed: July 17, 2003
    Date of Patent: July 25, 2006
    Assignee: LSI Logic Corporation
    Inventors: Andrey A. Nikitin, Alexander E. Andreev
  • High speed serial interface test
    Patent number: 7082557
    Abstract: A high speed, two-way serial interface with a scrambler and de-scrambler may be tested by sending a single word repeatedly through the scrambler to create a pseudo-random sequence. The pseudo-random sequence is then passed through the transmitter and looped back through the receiver of the serial interface. The pseudo-random sequence is then descrambled and compared to the input word. Since the input sequence is only a single word rather than a series of words, the comparison is very simple and capable of being performed within the serial interface itself without the need for external test equipment.
    Type: Grant
    Filed: June 9, 2003
    Date of Patent: July 25, 2006
    Assignee: LSI Logic Corporation
    Inventors: Steven Schauer, Kevin Campbell
  • Method and apparatus for measuring high speed glitch energy in an integrated circuit
    Patent number: 7081762
    Abstract: A method and apparatus are provided for measuring high speed glitch energy between first and second. The method and apparatus induce a change in charge on the first node from a first charge level to a second charge level with glitch energy supplied by the second node. An amount of charge is then supplied to the first node to restore the charge on the first node from the second charge level toward the first charge level. A representation of the amount of charge supplied to the first node is measured.
    Type: Grant
    Filed: July 31, 2003
    Date of Patent: July 25, 2006
    Assignee: LSI Logic Corporation
    Inventors: John L. McNitt, Scott C. Savage
  • Built-in functional tester for search engines
    Patent number: 7082561
    Abstract: A search engine apparatus having a built-in functional test may include an input generator, a search engine, a pseudo search engine and a comparator. The inputs generator is suitable for generating outputs including commands and points associated with the commands. The search engine and the pseudo search engine are communicatively coupled to the inputs generator. The search engine suitable for performing search and edit operations and the pseudo search engine is suitable for simulating the search engine by generating pseudo search engine outputs. The comparator is communicatively coupled to the search engine and the pseudo search engine, and is suitable for comparing outputs received from the search engine and pseudo search engine.
    Type: Grant
    Filed: April 30, 2002
    Date of Patent: July 25, 2006
    Assignee: LSI Logic Corporation
    Inventors: Alexander E. Andreev, Anatoli A. Bolotov, Nikola Radovanovic
  • Automated analysis of RTL code containing ASIC vendor rules
    Patent number: 7082584
    Abstract: A method of automatically analyzing RTL code includes receiving as input RTL code for an integrated circuit design. An RTL platform is selected that incorporates design rules for a vendor of the integrated circuit design. The design rules are displayed from the RTL platform on a graphic user interface. A number of the design rules are selected from the graphic user interface. An analysis is performed in the RTL platform of the RTL code for each of the selected design rules. A result of the analysis is generated as output for each of the selected design rules.
    Type: Grant
    Filed: April 30, 2003
    Date of Patent: July 25, 2006
    Assignee: LSI Logic Corporation
    Inventors: Juergen Lahner, Kiran Atmakuri, Kavitha Chaturvedula, Balamurugan Balasubramanian, Krishna Devineni, Srinivas Adusumalli, Randall P. Fry, Gregory A. Pierce
  • Method of generating a schematic driven layout for a hierarchical integrated circuit design
    Patent number: 7082589
    Abstract: A method of generating a schematic driven layout for an integrated circuit design includes steps of: (a) receiving as input a representation of a integrated circuit design comprising a hierarchy of blocks; (b) selecting a block in the hierarchy of blocks that requires a physical design and that contains no missing components; (c) generating a physical design for the selected block so that the selected block is no longer a missing component of any other block; and (d) repeating steps (b) and (c) until a physical design has been generated for each block in the hierarchy of blocks.
    Type: Grant
    Filed: November 10, 2003
    Date of Patent: July 25, 2006
    Assignee: LSI Logic Corporation
    Inventors: Michael J. Saunders, Norman E. Mause, C. Chip Brewster
  • Substrate via layout to improve bias humidity testing reliability
    Patent number: 7081672
    Abstract: A substrate is provided, which has a pattern of voltage supply vias extending through at least a portion of the substrate. Each of a plurality of the voltage supply vias is surrounded by four of the voltage supply vias of a same polarity in four orthogonal directions and by four voltage supply vias of an opposite polarity in four diagonal directions.
    Type: Grant
    Filed: March 7, 2005
    Date of Patent: July 25, 2006
    Assignee: LSI Logic Corporation
    Inventors: Anand Govind, Aritharan Thurairajaratnam, Farshad Ghahghahi
  • Interconnect dielectric tuning
    Patent number: 7081406
    Abstract: An improvement to a method of forming an integrated circuit. An etch stop layer is formed to overlie the front end processing layers of the integrated circuit. Support structures are formed that are disposed so as to support electrically conductive interconnects on various levels of the integrated circuit. Substantially all of the non electrically conductive layers above the etch stop layer that were formed during the fabrication of the interconnects are removed.
    Type: Grant
    Filed: August 10, 2004
    Date of Patent: July 25, 2006
    Assignee: LSI Logic Corporation
    Inventors: Wai Lo, Hong Lin, Shiqun Gu, Wilbur G. Catabay, Zhihai Wang, Wei-Jen Hsia
  • Method for growing thin films
    Patent number: 7081296
    Abstract: A method of forming a layer over a substrate is provided. Generally, a layer of a first reactive species is deposited over the substrate. The layer of the first reactive species is reacted with a second reactive species to create a first product. Unreacted reactive species is preferentially desorbed leaving a layer of the first product.
    Type: Grant
    Filed: March 16, 2004
    Date of Patent: July 25, 2006
    Assignee: LSI Logic Corporation
    Inventors: Sheldon Aronowitz, Vladimir Zubkov, Richard Schinella
  • Pad conditioner setup
    Patent number: 7081037
    Abstract: A method for inspecting the uniformity of the pressure applied between a conditioner and a polishing pad on a chemical mechanical polisher. A sheet of pressure sensitive material is placed between the conditioner and the polishing pad, and the conditioner is lowered onto the sheet of pressure sensitive material. A desired degree of pressure is applied between the conditioner and the polishing pad, thereby creating an impression in the sheet of pressure sensitive material, and the conditioner is lifted from the sheet of pressure sensitive material. The sheet of pressure sensitive material is inspected to determine the uniformity of the pressure applied between the conditioner and the polishing pad.
    Type: Grant
    Filed: September 22, 2003
    Date of Patent: July 25, 2006
    Assignee: LSI Logic Corporation
    Inventors: Michael J. Berman, Jan Fure
  • Energy recycling in clock distribution networks using on-chip inductors
    Patent number: 7082580
    Abstract: A clock distribution network for an integrated circuit includes a clock driver for generating a clock signal having a selected clock frequency, a clock net coupled to the clock driver wherein the clock net has a capacitive reactance, and an inductor coupled to the clock net wherein the inductor has an inductive reactance that is substantially equal to the capacitive reactance of the clock net at the selected clock frequency to minimize clock driver output current.
    Type: Grant
    Filed: February 10, 2003
    Date of Patent: July 25, 2006
    Assignee: LSI Logic Corporation
    Inventors: Payman Zarkesh-Ha, William Loh
  • Advanced storage controller
    Patent number: 7082390
    Abstract: The present invention is directed to an advanced storage controller that is capable of providing parallel processing capabilities to a host processing system connected storage system to increase performance, functionality and reliability of the entire computing system. The advanced storage controller comprises at least one input interface and at least one output interface, a host device simulation component, a cache device component, a physical device component and a management component. Such an advanced storage controller further, includes one or more processor elements and storage elements, which may be shared by the components or dedicated to one component. Additionally, the advanced storage controller is scalable by the static or dynamic addition of components, processors and/or memory.
    Type: Grant
    Filed: April 30, 2002
    Date of Patent: July 25, 2006
    Assignee: LSI Logic Corporation
    Inventor: James R. Bergsten
  • Method for reducing a parasitic graph in moment computation in VLSI systems
    Patent number: 7082583
    Abstract: An improved method for interconnect delay analysis for VLSI circuits reduces a parasitic graph for moment computation by eliminating one or more nodes in the graph. The elimination process is performed based upon the degree of the nodes. By eliminating nodes in this fashion, the computation complexity is significantly reduced. With this elimination process, resistor loops and crossed loops can also be solved. The order in which the nodes are eliminated is optimized using the depth-first-search method on the parasitic graphs, further reducing the computation complexity. The method provides a consistent functional interface, applicable to different circuit model structures. In addition, the method accounts for coupling capacitance between interconnects.
    Type: Grant
    Filed: November 20, 2002
    Date of Patent: July 25, 2006
    Assignee: LSI Logic Corporation
    Inventors: Weiqing Guo, Sandeep Bhutani
  • Online RAID migration without non-volatile memory
    Patent number: 7082498
    Abstract: A method for providing online raid migration without non-volatile memory employs reconstruction of the RAID drives. In this manner, the method of the present invention protects online migration of data from power failure with little or no performance loss so that data can be recovered if power fails while migration is in progress, and migration may be resumed without the use of non-volatile memory.
    Type: Grant
    Filed: November 4, 2002
    Date of Patent: July 25, 2006
    Assignee: LSI Logic Corporation
    Inventors: Paresh Chatterjee, Parag Maharana, Sumanesh Samanta
  • Local interconnect for integrated circuit
    Patent number: 7081379
    Abstract: An integrated circuit having a gate region, a source drain region, and an electrically nonconductive spacer separating the gate region and the source drain region. A local interconnect electrically connects the gate region to the source drain region across the electrically nonconductive spacer. The local interconnect is formed of a semiconducting material reacted with a metal. The local interconnect may be formed by implanting a precursor species into the electrically nonconductive spacer. A metal layer is deposited over at least the electrically nonconductive spacer, and the integrated circuit is heated to form an electrically conductive local interconnect from the metal layer and the precursor species implanted in the electrically nonconductive spacer.
    Type: Grant
    Filed: February 15, 2005
    Date of Patent: July 25, 2006
    Assignee: LSI Logic Corporation
    Inventors: Jeffrey F. Hanson, Derryl D. J. Allman
  • Method and/or apparatus for implementing enhanced device identification
    Patent number: 7082522
    Abstract: An apparatus comprising a first circuit, a second circuit and a third circuit. The first circuit may be configured to present device information in response to one or more externally generated signals. The second circuit may be configured to store the device information. The third circuit may have (i) a first mode configured to program the device information into the second circuit and (ii) a second mode configured to transfer the device information from the second circuit to the first circuit.
    Type: Grant
    Filed: July 9, 2002
    Date of Patent: July 25, 2006
    Assignee: LSI Logic Corporation
    Inventor: Jeffrey K. Whitt
  • Method to maintain data integrity during flash file transfer to raid controller flash using a terminal emulation program
    Patent number: 7080199
    Abstract: A method and system which uses the method maintains data integrity during file transfers from a local drive medium to a RAID controller flash memory. A signature is added to the data file in the local drive by a utility program. The signature is multibyte and, preferably, is either four or eight bytes long. The RAID controller is loaded with software that traverses the data file until the signature is found. The RAID controller software discards the signature and any after patched data and stores the stripped off data into its flash memory. The utility program overcomes potential incompatibility between the file transfer protocol and a terminal emulation program.
    Type: Grant
    Filed: July 15, 2003
    Date of Patent: July 18, 2006
    Assignee: LSI Logic Corporation
    Inventor: Jinchao Yang
  • Modified binary search for optimizing efficiency of data collection time
    Patent number: 7079963
    Abstract: A method for a modified binary search includes steps of: selecting a parameter having a distribution of values, selecting a probability density function representative of the distribution of values of the selected parameter, defining a substantially equal probability weighted binary test interval from the probability density function for each of a selected number of test intervals over a selected test range, translating the weighted binary test intervals to obtain a highest resolution at a target point of the selected parameter, and skewing the translated and weighted binary test intervals by a selected scaling function to generate a modified binary test interval for each of the selected number of test intervals over the selected test range.
    Type: Grant
    Filed: April 14, 2003
    Date of Patent: July 18, 2006
    Assignee: LSI Logic Corporation
    Inventors: Cary Gloor, Robert Benware, Robert Madge
  • Methodology to accurately test clock to signal valid and slew rates of PCI signals
    Patent number: 7078924
    Abstract: A method for populating and depopulating components of negligible impedance facilitates the testing of circuit boards. The test circuitry may be formed upon the circuit board under test. Testing may be performed with great accuracy for the time between the triggering edge of a clock pulse and a resulting valid signal change. Slew rates of bus signals may be more easily measured.
    Type: Grant
    Filed: September 20, 2002
    Date of Patent: July 18, 2006
    Assignee: LSI Logic Corporation
    Inventors: Keith Grimes, Raymond S. Rowhuff, William Schmitz
  • Method of qualifying a process tool with wafer defect maps
    Patent number: 7079966
    Abstract: A method of qualifying a process tool includes steps of: (a) finding a plurality of pre-scan defect locations on a surface of a semiconductor wafer; (b) subjecting the semiconductor wafer to processing by the process tool; (c) finding a plurality of post-scan defect locations on the surface of the semiconductor wafer; and (d) calculating a plurality of defect locations added by the process tool from the pre-scan defect locations and the post-scan defect locations.
    Type: Grant
    Filed: September 8, 2003
    Date of Patent: July 18, 2006
    Assignee: LSI Logic Corporation
    Inventors: John A. Knoch, Deborah A. Leek, Nathan Strader