Abstract: In described embodiments, effects of frequency and phase error introduced at the outer diameter or inner diameter of the disk when a read head is used to maintain timing lock while the write head is used to write new data might be eliminated with a simple compensation circuit. Compensation circuits, modules or methods receive as input information i) write head radial position (e.g., from a wedge number that indicates the circumferential position of the heads), and ii) read head and write head relative physical offset. The timing error is measured by the system and might be automatically adjusted by the appropriate amount in order to reduce or to eliminate the differential head error when a write event (as opposed to a read event) is activated.

Abstract: Disclosed is a closed-loop feedback system for controlling the soft error rate (SER) due to radiation strikes on electronic circuitry. A variable sensitivity soft error rate detector provides and output corresponding to the soft error rate. This output is supplied to a voltage control. The output of the voltage control is fed back to the sensitivity control of the sensor—thus forming a feedback loop. The output of the voltage control may be the power supply of the soft error rate sensor. The output of the soft error rate sensor may also be used to enable and disable fault tolerant schemes or alert a user.

Abstract: A method for activating and deactivating parameter sets during decoding of a bitstream for display, comprising the steps of: (A) tagging a first picture parameter information set associated with a first identification value as active in response to a reference to the first identification value in a bitstream; (B) changing the tag of the first picture parameter information set from active to inactive and tagging a second picture parameter information set associated with a second identification value as active in response to a reference to the second identification value in the bitstream; and (C) tagging the second picture parameter information set as inactive and re-tagging the first picture parameter information set as active in response to a subsequent reference to the first identification value in the bitstream.

Abstract: Systems and methods for management of replicated storage. Features and aspects hereof provide management of data replication among a plurality of storage systems in a manner substantially transparent to host systems attached to the storage systems. The storage systems are coupled to one another through a replication link. One storage systems is designated the primary storage system and all others are designated secondary storage systems. A common logical volume is defined with a common logical volume device identifier used by all of the replicating storage systems of a replication group and their respective attached host systems. The primary storage system processes I/O requests directed to the logical volume by accessing its physical storage volume and forwarding the request to be replicated to all secondary storage systems over the replication link. Secondary storage systems process I/O requests by shipping them over the replication link to the primary storage system for processing.

Abstract: A system for controllably generating jitter in a serial data stream includes a frequency generator and first and second mixers. The frequency generator is configured to output in-phase and quadrature local oscillator signals with a local oscillator frequency of at least about 5 MHz. The local oscillator frequency varies between a selectable minimum frequency and a selectable maximum frequency. The first mixer is configured to mix a fixed frequency clock signal with the in-phase local oscillator signal to output a first mixer output. The second mixer is configured to mix the fixed frequency clock signal with the quadrature local oscillator signal to output a second mixer output. An adder is configured to add the first and second mixer outputs to produce a frequency-modulated clock signal with a frequency that is about the sum of the fixed frequency and the local oscillator frequency and includes a periodic jitter.

Abstract: Techniques are provided for prolonging a lifetime of memory by controlling operations that affect the lifetime of the memory. At least one aspect associated with the memory lifetime is identified and at least one of the operations is delayed, based on the at least one aspect. The operations include a write operation, an erase operation, a program operation, and/or any other operation that is capable of reducing the memory lifetime.

Abstract: An apparatus comprising a control circuit, a buffer circuit and a memory. The control circuit may be configured to present a plurality of pairs of signals in response to (i) one or more input signals operating at a first data rate and (ii) an input clock signal operating at a second data rate. The second signal in each of the pairs comprises a clock signal operating at the second data rate. The buffer circuit may be configured to generate a buffered signal in response to each of the pairs of signals. Each of the buffered signals operates at the second data rate. The memory may be configured to read and write data at the second data rate in response to the buffered signals.

Abstract: The present invention is directed to a method for providing Quality Of Service (QoS)-based storage tiering and migration in a storage system. The method allows for configurable application data latency thresholds to be set on a per user basis and/or a per application basis so that a storage tiering mechanism and/or a storage migrating mechanism may be triggered for moving application data to a different class of storage.

Abstract: A comparator determines the fidelity of a response vector received from a memory under test. The comparator includes a first logic gate configured to output a first value that is the logical OR of a first proper subset of bits of the response vector. A second logic gate is configured to output a second value that is the logical NAND of the proper subset of bits. A first multiplexer is configured to select between the first and second values based on the value of a first bit of a check vector corresponding to the response vector.

Abstract: A hardware automated IO path, comprising a message transport unit for transporting an IO request to a local memory via a DMA operation and determining a LMID for associating with a request descriptor of the IO request; a fastpath engine for validating the request descriptor and creating a fastpath descriptor based on the request descriptor; a data access module for performing an IO operation based on the fastpath descriptor and posting a completion message into the fastpath completion queue upon a successful completion of the IO operation. The fastpath engine is further configured for: receiving the completion message, releasing the IO request stored in the local memory, and providing a reply message based on the completion message. The message transport unit is further configured for providing the reply message in response to the IO request.

Abstract: Techniques are provided for identifying at least one aspect associated with a lifetime of each of a plurality of memory devices. Further, data is moved between the plurality of memory devices, based on the at least one aspect.

Abstract: Disclosed is an internal cable system that communicates signals in an electronic device. The system uses a printed circuit board with active circuits that is connected to a standard communication cable. The printed circuit board is exposed to air flow from the cooling system of the electronic device for proper operation of the active components of the active circuits on the printed circuit board. The standard cable may include a SCSI internal cable or other similar signal communication cables. Signal integrity is enhanced using the active circuits that are mounted on the printed circuit board. Power is supplied to the printed circuit board through inactive conductors in the cable or conductors that would otherwise be used for grounding.

Abstract: A method comprising the steps of (A) generating a code, (B) applying one or more constraint constructs to the code, (C) generating a coverage code and a second code in response to applying the constraint constructs to the code, (D) generating a third code in response to the code, and (E) generating one or more assembly language tests in response to the second code.

Abstract: A system, method, and computer program product are provided for sending de-allocation status information. In use, a de-allocation status of at least a portion of memory associated with a logical block address is determined. Additionally, de-allocation status information is generated, based on the determination. Furthermore, the de-allocation status information is sent to a device.

Abstract: Techniques for writing data to different portions of storage devices based on write frequencies are disclosed. Frequencies of data writes to various portions of a memory are monitored. The memory includes various storage technologies. Each portion includes one of the storage technologies and has a respective lifetime. An order that the portions are written into and recycled is dynamically managed to equalize respective life expectancies of the portions in view of differences in endurance values of the portions, the monitored frequencies of data writes, and the lifetimes. In some embodiments, the storage technologies include Single-Level Cell (SLC) flash memory storage technology and Multi-Level Cell (MLC) flash memory storage technology. The SLC and MLC flash memory storage technologies are optionally integrated in one device. In some embodiments, the storage technologies include two or more different types of SLC flash memory storage technologies, optionally integrated in one device.

Abstract: Storage systems configured for improved N-way connectivity among all of a plurality of storage controllers and all of a plurality of storage devices in the system. All controllers of the storage system are coupled through a switched fabric communication medium to all of the storage devices of the storage system. Thus, the back-end interface of each storage controller of the storage system is used for all communications with any of the storage devices as well as for any communications among the controllers to coordinate the N-way distribution of stored data in a declustered RAID storage environment. This use of the back-end channel for all storage controller to storage device N-way connectivity as well as controller to controller N-way connectivity eliminates the need for a dedicated inter-controller interface for such N-way connectivity and eliminates the over-utilization of a front-end (e.g., network) communication path for providing N-way connectivity in the storage system.

Abstract: A controller is provided that receives a single enclosure management (EM) serial bit stream from an expander or other device and divides the EM serial bit stream into multiple EM serial bit streams for delivery to multiple respective midplanes or backplanes. In this way, a separate EM serial bit stream is provided to each midplane or backplane without having to increase the number of ports that are available on the expander or other device that interfaces with the backplane or midplane.

Abstract: Embodiments of the invention include a method, apparatus and system for providing a Serial Attached SCSI (SAS) domain management application using a domain overlay architecture. The method includes comparing user constructs or data sets defining an existing domain overlay with device data that identifies various network devices in at least one SAS domain, and binding the existing domain overlay to an SAS domain if the existing domain overlay and the SAS domain are uniquely associated with one another. The method also includes creating a new domain overlay that is uniquely associated with an SAS domain for any SAS domain that is not bound to an existing domain overlay. A domain overlay and an SAS domain are not uniquely associated with one another unless the domain overlay references only network devices within the SAS domain and the network devices within the SAS domain are referenced only by the domain overlay.

Abstract: An electronic device includes a heat dissipating component located over a substrate. An isolation trench is formed in the substrate adjacent the component. A contact region of the substrate is bounded by the trench. An electrically isolated contact is located over and in contact with the contact region. The electrically isolated contact and the contact region provide a thermally conductive path to the substrate.