Patents Assigned to LSI
-
Patent number: 8254440Abstract: An apparatus configured to process a digital video signal comprising an input circuit, a processing circuit and an encoder circuit. The input circuit may be configured to present a digital video signal comprising a plurality of frames. The processing circuit may be configured to detect scene changes in the digital video signal by analyzing (i) a current one of the plurality of frames and (ii) two or more other frames. The encoder circuit may be configured to generate an encoded signal in response to the digital video signal and the scene changes. The two or more other frames may comprise (i) a first window of frames that are processed before the current frame and (ii) a second window of frames that are processed after the current frame. The processing circuit may also detect the scene changes by analyzing changes between the first window and the second window.Type: GrantFiled: December 4, 2007Date of Patent: August 28, 2012Assignee: LSI CorporationInventors: Benoit F. Bazin, Cecile M. Foret
-
Patent number: 8255644Abstract: Described embodiments provide a memory system including a plurality of addressable memory arrays. Data in the arrays is accessed by receiving a logical address of data in the addressable memory array and computing a hash value based on at least a part of the logical address. One of the addressable memory arrays is selected based on the hash value. Data in the selected addressable memory array is accessed using a physical address based on at least part of the logical address not used to compute the hash value. The hash value is generated by a hash function to provide essentially random selection of each of the addressable memory arrays.Type: GrantFiled: May 18, 2010Date of Patent: August 28, 2012Assignee: LSI CorporationInventors: David P. Sonnier, Michael R. Betker
-
Patent number: 8251552Abstract: Lighting apparatus and structures are described that are adapted for installation in housings. The housings can be pre-existing ones, such as those installed for high-intensity discharge (HID) or other types of lighting. The lighting apparatus can include a light unit (e.g., luminaire) with desired type of light source(s), for example, an array of LEDs. The apparatus can include structures that are adapted for use with the housings such that installation of a light unit requires a minimum of user effort and time. Such lighting apparatus, and related installation methods, can accordingly provide for high-efficiency lighting. Related assembly and installation techniques are also described.Type: GrantFiled: March 24, 2010Date of Patent: August 28, 2012Assignee: LSI Industries, Inc.Inventors: Rob Allen Rooms, John D. Boyer
-
Patent number: 8255634Abstract: Apparatus and methods for improved efficiency in accessing meta-data in a storage controller of a virtualized storage system. Features and aspects hereof walk/retrieve meta-data for one or more other I/O requests when retrieving meta-data for a first I/O request. The meta-data may include mapping information for mapping logical addresses of the virtual volume. Meta-data may also include meta-data associated with higher level, enhanced data services provide by or in conjunction with the storage system. Enhanced data services may include features for synchronous mirroring of a volume and/or management of time-based snapshots of the content of a virtual volume.Type: GrantFiled: August 11, 2010Date of Patent: August 28, 2012Assignee: LSI CorporationInventor: Howard Young
-
Publication number: 20120215939Abstract: In one embodiment of a header-compression method, a timestamp value is divided by a stride value using a plurality of binary-shift operations corresponding to a Taylor expansion series of the reciprocal stride value in a base of ½. When the division-logic circuitry of an arithmetic logic unit in the corresponding communication device is not designed to handle operands that can accommodate the length of the timestamp and/or stride values, the header-compression method can advantageously be used to improve the speed and efficiency of timestamp compression in communication devices.Type: ApplicationFiled: February 22, 2011Publication date: August 23, 2012Applicant: LSI CORPORATIONInventor: Xiaomin Lu
-
Publication number: 20120215824Abstract: In one embodiment of a header-compression method, a 32-bit timestamp value is divided by a 16- or 8-bit stride value using a plurality of 16/8-bit division operations, each performed using a corresponding hardware instruction issued to an arithmetic logic unit (ALU) of the corresponding communication device, such as an access terminal or a base station of a communication system. When specialized 32/16-bit and/or 32/8-bit division-logic circuitry is not available in the ALU, embodiments of the header-compression method can advantageously be used to improve the speed and efficiency of timestamp compression in communication devices.Type: ApplicationFiled: February 22, 2011Publication date: August 23, 2012Applicant: LSI CORPORATIONInventor: Xiaomin Lu
-
Publication number: 20120212256Abstract: A voltage translator circuit includes an input stage adapted for receiving an input signal referenced to a first voltage supply, a first latch circuit adapted for connection with a second voltage supply and operative to at least temporarily store a logic state of the input signal, and a voltage clamp coupled between the input stage and the first latch circuit. The voltage clamp is operative to set a maximum voltage across the input stage to a prescribed level. The voltage translator circuit generates a first output signal at a first output formed at a junction between the first latch circuit and the voltage clamp. A second latch circuit is connected to the first output in a feedback configuration. The second latch circuit is operative to retain a logical state of the first output signal as a function of at least a first control signal supplied to the second latch circuit regardless of a state of the first voltage supply.Type: ApplicationFiled: February 18, 2011Publication date: August 23, 2012Applicant: LSI CorporationInventors: Peter J. Nicholas, John Christopher Kriz, Dipankar Bhattacharya, James John Bradley
-
Publication number: 20120212878Abstract: An electronic device package includes first and second electrodes of a package substrate. The first electrode has fingers formed from a first metal level and is configured to operate at a first DC potential. The second electrode has fingers formed from the first metal level interdigitated with the fingers of the first electrode. A via conductively connects the second electrode to a second metal level. The second metal level is configured to operate at a second DC potential. The first and second DC potentials are thereby capacitively coupled through the interdigitated electrodes.Type: ApplicationFiled: February 22, 2011Publication date: August 23, 2012Applicant: LSI CorporationInventors: Shawn M. Logan, Ellis E. Nease
-
Publication number: 20120212958Abstract: A lighting apparatus having a base member and a directional member are shown and described. The base member includes a first surface having a plurality of reflective elements extending therefrom. The base member also including a plurality of openings arranged in a pattern. Each openings is configured to receive a respective light source. The directional member has a portion of a reflective surface positioned relative to at least one opening to reflect light radiating from a lighting source disposed within the opening towards a portion of at least one of the reflective elements extending from the base member.Type: ApplicationFiled: March 26, 2012Publication date: August 23, 2012Applicant: LSI INDUSTRIES, INC.Inventors: John D. Boyer, James G. Vanden Eynden
-
Patent number: 8250589Abstract: A method may include defining an interface class including a static member having an implementation pointer. The method may also include loading a main code segment including a stub implementation of the interface class. Additionally, the method may include instantiating the stub implementation of the interface class to provide a stub implementation object. The stub implementation of the interface class may include a first constructor configured to set the implementation pointer to the stub implementation object. Further, the method may include loading a dynamic library including a real implementation of the interface class. Still further, the method may include instantiating the real implementation of the interface class to provide a real implementation object. The real implementation of the interface class may include a second constructor configured to set the implementation pointer to the real implementation object.Type: GrantFiled: April 3, 2009Date of Patent: August 21, 2012Assignee: LSI CorporationInventor: James A. Lynn
-
Patent number: 8249063Abstract: A communication device comprises a signal combiner, first storage elements, second storage elements and a controller. The signal combiner is configured to combine overhead information with additional information in forming a frame of a signal. The first storage elements are adapted to receive respective portions of a given block of the overhead information to be applied to the signal combiner, and the second storage elements are coupled between respective ones of the first storage elements and respective inputs of the signal combiner. The controller is operative to monitor a count of portions of the frame as the frame is formed by the signal combiner and to control loading of the portions of the given block of the overhead information into the second storage elements from the first storage elements responsive to the monitored count.Type: GrantFiled: June 30, 2009Date of Patent: August 21, 2012Assignee: LSI CorporationInventors: Cheng Gang Duan, Lin Hua, Ze Mian Huang, Michael S. Shaffer, Tao Wang
-
Patent number: 8250392Abstract: In described embodiments, turn-on time for active portions of an Energy Efficient Ethernet (EEE) device is improved by storing energy in a corresponding capacitor bank through a bidirectional device from a certain node in the device during an active state, continuing to store the energy when the device enters a Low Power Idle (LPI) state, and then allowing the energy to return to the node through the bidirectional device when the device returns to an active state. During active mode, the bidirectional device controls the capacitor bank so as to charge relatively slowly to store energy, and when the device transitions to LPI, the charge is maintained in the capacitor bank. When the device returns to the active state, the bidirectional device allows the capacitor bank to discharge relatively rapidly to the node, thereby improving the turn-on time of the circuit elements coupled to the node.Type: GrantFiled: November 20, 2009Date of Patent: August 21, 2012Assignee: LSI CorporationInventor: Roger Fratti
-
Patent number: 8250129Abstract: An apparatus and method are provided in various illustrative embodiments for an integrated circuit chip that provides a fast, compact, and cryptographically strong random number generator. In one illustrative embodiment, an apparatus includes an initial random source, and a post-processing block in communicative connection with the initial random source. The post-processing block is configured to receive signals from the initial random source, to apply one or more finite field operations to the signals to generate an output, and to provide an output signal based on the output via an output channel, in this illustrative embodiment.Type: GrantFiled: June 22, 2007Date of Patent: August 21, 2012Assignee: LSI CorporationInventors: Sergey Gribok, Alexander Andreev, Sergey Gashkov
-
Patent number: 8250431Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing circuit is disclosed that includes a first data detection circuit that applies a phase dependent data detection algorithm to a data set such that a first output of the first data detection circuit varies depending upon a phase of the data set presented to the first data detection circuit. A first phase of the data set is presented to the first data detection circuit. The circuits further include a decoder circuit that applies a decoding algorithm to the first output to yield a decoded output, and a phase shift circuit that phase shifts the decoded output such that a second phase of the data set is provided as a phase shifted output.Type: GrantFiled: July 30, 2009Date of Patent: August 21, 2012Assignee: LSI CorporationInventors: Shaohua Yang, Zongwang Li, Weijun Tan, Kelly Fitzpatrick
-
Patent number: 8250434Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing circuit is disclosed that includes an increased iteration enable signal, a first detector circuit, a second detector circuit, and a data decoding circuit. The first detector circuit receives a data set and performs a data detection on the data set to provide a detected data set. The data decoding circuit receives a derivative of the detected data set and performs a decoding process to provide a decoded data set. The decoded data set is provided to the second detector circuit based at least in part on an assertion level of the increased iteration enable signal.Type: GrantFiled: June 18, 2009Date of Patent: August 21, 2012Assignee: LSI CorporationInventors: Shaohua Yang, Yuan Xing Lee, Changyou Xu, Richard Rauschmayer, Harley Burger, Kapil Gaba
-
Publication number: 20120210287Abstract: Methods and apparatus for increasing the accuracy of timing characterization of a circuit including at least one cell in a cell library are provided. One method includes the steps of: performing cell library timing characterization for the cell for prescribed first and second temperatures, the first and second temperatures corresponding to minimum and maximum temperatures of operation of the circuit, respectively; selecting one or more additional temperatures between the first and second temperatures; performing cell timing characterization for each process, voltage and temperature (PVT) corner at the one or more additional temperatures, as well as at the first and second temperatures; and performing timing sign-off for each PVT corner using the one or more additional temperatures, the timing sign-off being based at least in part on the timing characterization for each PVT corner.Type: ApplicationFiled: April 23, 2012Publication date: August 16, 2012Applicant: LSI CORPORATIONInventor: Alexander Tetelbaum
-
Patent number: 8243804Abstract: A method for implementing motion estimation comprising the steps of (A) performing a motion estimation search on one or more blocks of sub-sampled images to generate a first plurality of motion vector scores, (B) applying a first adjustable bias to any one or more of said first plurality of motion vector scores with a lowest sum of absolute differences score, (C) selecting a motion vector with a lowest adjusted score in response to applying the first adjustable bias, (D) performing a motion estimation search on one or more blocks of non-sub-sampled images to generate a second plurality of motion vector scores with the selected motion vector with the lowest adjusted score, (E) applying a second adjustable bias to any one or more of the second plurality of motion vector scores with the lowest sum of absolute differences score and (F) selecting a final motion vector for each target block position.Type: GrantFiled: December 1, 2005Date of Patent: August 14, 2012Assignee: LSI CorporationInventors: Kourosh Soroushian, Soo-Chul Han
-
Patent number: 8243737Abstract: Described embodiments provide a first-in, first-out (FIFO) buffer for packet switching in a crossbar switch with a speedup factor of m. The FIFO buffer comprises a plurality of registers configured to receive N-bit portions of data in packets and a plurality of one-port memories, each having width W segmented into S portions a width W/S. A first logic module is coupled to the registers and the one-port memories and receives the N-bit portions of data in and the outputs of the registers. A second logic module coupled to the one-port memories constructs data out read from the one-port memories. In a sequence of clock cycles, the N-bit data portions are alternately transferred from the first logic module to a segment of the one-port memories, and, for each clock cycle, the second logic module constructs the data out packet with output width based on the speedup factor of m.Type: GrantFiled: March 22, 2010Date of Patent: August 14, 2012Assignee: LSI CorporationInventors: Ting Zhou, Sheng Liu, Ephrem Wu
-
Patent number: 8245098Abstract: In one embodiment, an LDPC decoder has a plurality of check-node units (CNUs) and a controller. Initially, the CNUs generate check-node messages based on an initial offset value selected by the controller. If the decoder converges on a trapping set, then the controller selects new offset values for missatisfied check nodes (MSCs), the locations of which are approximated, and/or unsatisfied check nodes (USCs). In particular, offset values are selected such that (i) the messages corresponding to the MSCs are decreased relative to the messages that would be generated using the initial offset value and/or (ii) the messages corresponding to the USCs are increased relative to the messages that would be generated using the initial offset value. Decoding is then continued for a specified number of iterations to break the trapping set. In other embodiments, the controller selects scaling factors rather than, or in addition to, offset values.Type: GrantFiled: August 11, 2009Date of Patent: August 14, 2012Assignee: LSI CorporationInventors: Yang Han, Kiran Gunnam, Shaohua Yang, Hao Zhong, Nils Graef, Yuan Xing Lee
-
Patent number: 8245112Abstract: A flash-memory system is organized into a plurality of blocks and a plurality of pages in each block, each page having 2N data locations and K spare locations. At least one page in the memory has 2M?1 user data sectors and each sector has 2N-M+L locations therein. Error-correction code (ECC) data related to the user data is calculated and stored in at least the 2M user data locations unused by the 2M?1 user data sectors. Because L is at least 1 but less than 2N-M (N>M), at least a portion of one user data sector is stored in the spare memory locations. Additional locations in each page are available to allow for the ECC data to have additional redundancy bits added per sector, thereby making the flash memory system more robust and reliable.Type: GrantFiled: June 4, 2009Date of Patent: August 14, 2012Assignee: LSI CorporationInventors: Michael Hicken, Martin Dell