Patents Assigned to LSI
  • Patent number: 8284882
    Abstract: Methods and apparatus are provided for CDR and equalization update qualification. A block of received data comprising a plurality of multiple tone patterns is processed. Equalization adaptation and/or updates to a timing recovery process can be selectively disabled if one or more of the multiple tone patterns exceed a corresponding predefined threshold.
    Type: Grant
    Filed: June 25, 2009
    Date of Patent: October 9, 2012
    Assignee: LSI Corporation
    Inventors: Gregory A. Kleese, Mohammad S. Mobin, Kenneth W. Paist
  • Patent number: 8285934
    Abstract: A method of configuring a storage device is disclosed. The method generally includes the steps of (A) receiving a single data unit over a communication network, the data unit (i) being transferred via the communication network using a standard communication protocol, (ii) defining both (a) a plurality of new configuration items that define a new configuration of the storage device and (b) a command to be performed by the storage device and (iii) having a standard markup language format, (B) calculating at least one configuration change from a plurality of current configuration items to the new configuration items, the current configuration items defining a current configuration of the storage device, (C) adjusting the storage device into the new configuration based on the at least one configuration change and (D) performing a requested operation with the storage device in the new configuration in response to the command.
    Type: Grant
    Filed: December 13, 2011
    Date of Patent: October 9, 2012
    Assignee: LSI Corporation
    Inventors: Partha P. Porel, Tanmoy Sil
  • Patent number: 8285892
    Abstract: An apparatus comprising an arbiter circuit, a protocol engine circuit and a channel router circuit. The arbiter circuit may be configured to determine a winning channel from a plurality of channel requests based on a first criteria. Each of the plurality of channel requests may represent a burst of data having a fixed length aligned to an address boundary of a memory. The protocol engine circuit may be configured to receive a signal from the arbiter circuit indicating the winning channel. The protocol engine circuit may also be configured to perform a memory protocol at a granularity equal to the burst of data. The channel router circuit may be configured to present the plurality of channel requests to the arbiter circuit and the protocol engine circuit.
    Type: Grant
    Filed: August 17, 2010
    Date of Patent: October 9, 2012
    Assignee: LSI Corporation
    Inventors: Eskild T. Arntzen, Sheri L. Fredenberg, Jackson L. Ellis, Robert W. Warren
  • Patent number: 8283713
    Abstract: An electronic device includes an active layer located over a substrate with the active layer having a logic circuit and an eDRAM cell. The electronic device also includes a first metallization level located over the active layer that provides logic interconnects and metal capacitor plates. The logic interconnects are connected to the logic circuit and the metal capacitor plates are connected to the eDRAM cell. The electronic device additionally includes a second metallization level located over the first metallization level that provides an interconnect connected to at least one of the logic interconnects, and a bit line that is connected to the eDRAM cell. A method of manufacturing an electronic device is also included.
    Type: Grant
    Filed: March 14, 2011
    Date of Patent: October 9, 2012
    Assignee: LSI Corporation
    Inventors: John G. Jansen, Chi-Yi Kao, Ce Chen, Shahriar Moinian
  • Publication number: 20120250177
    Abstract: A method and apparatus for transferring data. First data is transferred in a first direction on a surface of a selected magnetic disk in a plurality of magnetic disks using a first actuator assembly. Second data is transferred in a second direction on the surface of the selected magnetic disk in the plurality of magnetic disks using a second actuator assembly, while the first data is being transferred in the first direction by the first actuator assembly.
    Type: Application
    Filed: April 1, 2011
    Publication date: October 4, 2012
    Applicant: LSI CORPORATION
    Inventors: Vinay Ashok Somanache, Haribhai Somabhai Patel
  • Patent number: 8279950
    Abstract: Described embodiments provide a method and system for signal compensation in a SERDES communication system that includes monitoring the quality of a data signal after passing through a transmission channel. The quality of the data signal is monitored with at least one of a BER calculation algorithm and a received eye quality monitoring algorithm. Variations in channel length of the transmission channel are compensated for by i) adjusting a length of transmission line delay of the data signal from the transmission channel, ii) comparing the data signal quality with a threshold for the adjusted data signal; and iii) repeating i) and ii) until the data signal quality meets the threshold.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: October 2, 2012
    Assignee: LSI Corporation
    Inventors: Pervez M. Aziz, Adam Healey, Shawn Logan
  • Patent number: 8281214
    Abstract: The present invention is a programmable QC LDPC encoder for encoding user data. The encoder may be configurable for implementation with a read channel. The encoder may include a plurality of barrel shifter circuits. The barrel shifter circuits are configured for generating a plurality of parity bits based on interleaved user bits received by the encoder. The barrel shifter circuits are further configured for outputting the parity bits. The encoder may further include an encoder interleaver memory. The encoder interleaver memory may be communicatively coupled with the barrel shifter circuits and may receive the parity bits output from the barrel shifter circuits. The encoder interleaver may be configured for interleaving the parity bits. Further, the encoder may be configured for outputting the interleaved parity bits to a multiplexer. The barrel shifter circuits may generate the plurality of parity bits via an encoding algorithm: p=u*GT.
    Type: Grant
    Filed: October 17, 2008
    Date of Patent: October 2, 2012
    Assignee: LSI Corporation
    Inventors: Shaohua Yang, Changyou Xu, Richard Rauschmayer, Hao Zhong, Weijun Tan
  • Patent number: 8280347
    Abstract: A mobile device is configured with electrical circuitry that causes the transmit channel electrical circuitry of the transmitter (Tx) of the mobile device to be electrically coupled to the receive channel electrical circuitry of the receiver (Rx) of the mobile device when one or more predetermined conditions occur. The electrical coupling of the transmit channel circuitry to the receive channel circuitry causes the Rx to be sufficiently damaged to render the mobile device nonoperational, thereby preventing further use of the mobile device. The one or more predetermined conditions correspond to conditions that indicate the mobile device has been lost or stolen and/or that an unauthorized user is attempting to use the mobile device in some manner.
    Type: Grant
    Filed: July 22, 2009
    Date of Patent: October 2, 2012
    Assignee: LSI Corporation
    Inventors: Kouros Azimi, Anthony J. Grewe
  • Patent number: 8281054
    Abstract: Methods and apparatus for improved performance in communications between a SAS/STP initiator device and a plurality of SATA storage devices coupled with the initiator through an enhanced switching device. The switching device is enhanced in accordance with features and aspects hereof to receive a DMA SETUP FIS from a SATA storage device and to transmit multiple modified DMA SETUP FISs to the initiator where each modified DMA SETUP FIS comprises a subcount less than the maximum count in the received DMA SETUP FIS.
    Type: Grant
    Filed: August 30, 2010
    Date of Patent: October 2, 2012
    Assignee: LSI Corporation
    Inventor: Brian A. Day
  • Patent number: 8280715
    Abstract: A method may include receiving a first selection via a user interface comprising a hardware configuration for a simulated computer storage system, the hardware configuration including a plurality of hardware components. The method may also include receiving a second selection via the user interface comprising a storage configuration for the plurality of hardware components of the simulated computer storage system. Further, the method may include creating a storage configuration template utilizing the storage configuration. Additionally, the method may include associating the plurality of hardware components of the simulated computer storage system with the storage configuration template. Further, the method may include storing the plurality of hardware components of the simulated computer storage system and the associated storage configuration template.
    Type: Grant
    Filed: June 5, 2009
    Date of Patent: October 2, 2012
    Assignee: LSI Corporation
    Inventor: Martin Jess
  • Patent number: 8279731
    Abstract: An optical-disc writer writes extrinsic data to an optical disc. Extrinsic data can be written as (i) embedded marks (e.g., pits and lands) located outside the conventional readable area of a disc and/or (ii) alternative marks, such as surface marks located on a surface of the disc. In an optical-disc player having a disc-reading subsystem and a read controller, the disc-reading subsystem reads and relays the extrinsic data to the read controller, which controls the operations of the player based on the extrinsic data. For example, the writer prints extrinsic data, e.g., a barcode, on the surface of a software installation disc. The disc is inserted in the player and installation is commenced. The read controller instructs the disc-reading subsystem to read the extrinsic information. If the read controller determines that the extrinsic data was successfully read, then installation proceeds; otherwise, installation is halted.
    Type: Grant
    Filed: July 9, 2009
    Date of Patent: October 2, 2012
    Assignee: LSI Corporation
    Inventors: Roger A. Fratti, John A. Michejda
  • Publication number: 20120242327
    Abstract: A signal detector includes a summation unit connected to offset first and second input signals representing a differential input signal into two offset pairs of first and second signals. The signal detector also includes a detection unit connected to select the first signal from one of the offset pairs of first and second signals and the second signal from the other of the offset pairs in an overlap portion of the first and second signals to form a complementary pair of overlap signals and provide a differentially peak-detected output signal from the complementary pair of overlap signals. Additionally, the signal detector includes a comparator connected to provide a detection output signal corresponding to the differentially peak-detected output signal and a reference signal. A method of operating a signal detector is also included.
    Type: Application
    Filed: March 24, 2011
    Publication date: September 27, 2012
    Applicant: LSI Corporation
    Inventor: Zichuan Cheng
  • Patent number: 8275029
    Abstract: An apparatus comprises a summer suitable for subtracting a filtered feedback signal from an input; a symbol decision device suitable for receiving an output from the summer; a feedback filter suitable for filtering an output from the symbol decision device and for sending the filtered feedback signal to the summer, the feedback filter comprising an adjustable swing amplifier and an adjustable pole filter; and an adaptation algorithm suitable for simultaneously adapting both a pole setting and a swing setting based upon a least mean squared error criteria. The summer, the symbol decision device, and the feedback filter form a feedback circuit utilized to reconstruct an electrical signal distorted during transmission.
    Type: Grant
    Filed: October 3, 2007
    Date of Patent: September 25, 2012
    Assignee: LSI Corporation
    Inventors: Philip Jenkins, Cathy Ye Liu, Mark Marlett, Jeff Kueng
  • Patent number: 8275925
    Abstract: Methods and apparatus for improved performance in communications with a SATA target device. Features and aspects hereof provide for continuing DMA transfers from a storage controller (e.g., a SATA host or a SAS/STP initiator) to a SATA target device without regard to receipt of DMA ACTIVATE Frame Information Structures (FIS). Logic to implement these features may be provided by bridge logic within an enhanced SAS expander coupled with an enhanced SAS/STP initiator or may be provided by suitable logic in an enhanced SATA host coupled directly with an enhanced SATA target device. By continuing DMA transfer of data from the initiator/host to the SATA target device without regard to receipt of a DMA ACTIVATE FIS, more of the available bandwidth of the SAS/SATA communication link may be utilized. Other standard features of the SAS/SATA protocols provide for flow control to prevent overrun of the SATA target device's buffers.
    Type: Grant
    Filed: August 25, 2010
    Date of Patent: September 25, 2012
    Assignee: LSI Corporation
    Inventor: Brian A. Day
  • Patent number: 8275025
    Abstract: Methods and apparatus are provided for pseudo asynchronous testing of receive paths in serializer/deserializer (SerDes) devices. A SerDes device is tested by applying a source of serial data to a receive path of the SerDes device during a test mode. The receive path substantially aligns to incoming data using a bit clock. A phase is adjusted during the test mode of the bit clock relative to the source of serial data to evaluate the SerDes device. The source of serial data may be, for example, a reference clock used by a phase locked loop to generate the bit clock. The phase of the bit clock can be directly controlled during the test mode, for example, by a test phase control signal, such as a plurality of interpolation codes that are applied to an interpolator that alters a phase of the bit clock.
    Type: Grant
    Filed: February 27, 2009
    Date of Patent: September 25, 2012
    Assignee: LSI Corporation
    Inventors: Christopher J. Abel, Parag Parikh, Vladimir Sindalovsky
  • Patent number: 8269280
    Abstract: A technique for enhancing substrate bias of grounded-gate NMOS fingers (ggNMOSFET's) has been developed. By using this technique, lower triggering voltage of NMOS fingers can be achieved without degrading ESD protection in negative zapping. By introducing a simple gate-coupled effect and a PMOSFET triggering source with this technique, low-voltage triggered NMOS fingers have also been developed in power and I/O ESD protection, respectively. A semiconductor device which includes a P-well which is underneath NMOS fingers. The device includes an N-well ring which is configured so that the inner P-well underneath the NMOS fingers is separated from an outer P-well. The inner P-well and outer P-well are connected by a P-substrate resistance which is much higher than the resistance of the P-wells. A P+-diffusion ring surrounding the N-well ring is configured to connect to VSS, i.e., P-taps.
    Type: Grant
    Filed: May 18, 2011
    Date of Patent: September 18, 2012
    Assignee: LSI Corporation
    Inventor: Jau-Wen Chen
  • Patent number: 8270289
    Abstract: Methods and apparatus are provided for framing synchronization control for a framer/mapper/multiplexor (FMM) device with 1+1 and equipment protection. FMM device are disclosed that synchronize one or more internal signals by changing a phase of the one or more internal signals without changing a frequency of the one or more internal signals based on a desired phase at a destination of each of the one or more internal signals. A programmable synchronization signal may optionally be employed for the synchronization.
    Type: Grant
    Filed: February 27, 2009
    Date of Patent: September 18, 2012
    Assignee: LSI Corporation
    Inventors: Cheng Gang Duan, Lin Hua, Michael S. Shaffer, Tao Wang, Qian G. Xu
  • Patent number: 8271811
    Abstract: Apparatus and method for managing power consumption of circuits within a Serial Attached SCSI (SAS) device. A SAS device having a plurality of PHY logic circuits includes a queue manager and a power manager. The queue manager is operable to determine a current workload based on queued entries for the plurality of PHY logic circuits. Based on the current workload, the power manager is operable to set identified ones of the plurality of PHY logic circuits into a low power mode. In some embodiments, PHY logic circuits may be restored to full power operation responsive to changes in the current workload and/or responsive to receipt of a signal from another SAS device coupled to the SAS device. In other embodiments the power manager is further operable to manage power consumption of link and/or DMA logic circuits of the SAS device.
    Type: Grant
    Filed: November 5, 2009
    Date of Patent: September 18, 2012
    Assignee: LSI Corporation
    Inventors: Joshua P. Sinykin, Brian A. Day
  • Patent number: 8271922
    Abstract: A system and method for clock optimization to achieve timing signoff in an electronic circuit and an EDA tool that embodies the system or the method. In one embodiment, the system includes: (1) a clock cell identifier/sorter configured to identify at least some clock cells in a clock network associated with an electronic circuit design and sort the cells according to breadth, (2) a slack analyzer associated with the clock cell identifier/sorter and configured to identify flops that are downstream of the cells and determine a worst setup and hold timing slack thereof and (3) a clock cell delay adjuster associated with the slack analyzer and configured to adjust delays of the cells subject to the worst setup and hold timing slack.
    Type: Grant
    Filed: April 14, 2009
    Date of Patent: September 18, 2012
    Assignee: LSI Corporation
    Inventors: Bruce E. Zahn, Gerard M. Blair
  • Publication number: 20120230029
    Abstract: A lighting apparatus is shown and described. In one aspect, the lighting apparatus includes a light source, a plate, and frame. The light source can include one or more lighting elements that are in thermal communication with the light source. The plate can have a dissipative portion extending outward from a point of thermal communication between the plate and the light source. The frame can at least partially enclose the light source and may also be in thermal communication therewith.
    Type: Application
    Filed: May 17, 2012
    Publication date: September 13, 2012
    Applicant: LSI INDUSTRIES, INC.
    Inventors: James G. Vanden Eynden, James P. Sferra, Larry A. Akers, John D. Boyer