Abstract: Various embodiments of the present invention provide systems and methods for data processing system. As one example, a data processing circuit is described that includes an analog to digital converter, an online timing loop, and an offline timing loop. The analog to digital converter receives an analog input and provides a first series of data samples Each bit of the first series of data samples corresponds to the analog input at a time controlled by an updated sampling clock. The online timing loop modifies the updated sampling clock based at least in part upon a processed version of the first series of data samples. The offline timing loop interpolates a derivative of the first series of data samples to yield a second series of data samples that mimics a series of data samples corresponding to the analog input that were sampled using a free running clock.

Abstract: An apparatus comprising a memory array and a plurality of processing circuits. The memory array may be configured to store a plurality of data bits in a plurality of rows and a plurality of columns. A plurality of data words may be stored in a respective plurality of the columns. The plurality of processing circuits may each be configured to compare (i) a test bit of a plurality of bits of an input data word with (ii) a test bit of one of the plurality of columns to determine a match. The compare may occur on a first clock cycle of an input clock signal. Each of the plurality of processing circuits may be configured to power down a respective column of the memory array if the test bit of the input data word does not match the test bit of the column.

Abstract: A method for transcoding is disclosed. The method generally includes the steps of (A) generating a decoded frame by decoding an input video stream in an MPEG-2 format, the decoded frame including a plurality of decoded macroblocks; (B) determining a current search center to be used in encoding a current macroblock into an H.264 format, the current macroblock corresponding to a pair of the decoded macroblocks on consecutive macroblock rows, wherein when (i) the encoding uses a predictive field mode and (ii) a current field being encoded comprises a second field of a current frame and has a first field of the current frame as a reference field, the current search center comprises a temporally scaled version of a decoded motion vector from one of an upper macroblock of the pair and a lower macroblock in the pair; (C) generating a refined motion vector by searching in a temporal search direction about the current search center; and (D) generating an output video stream in the H.

Abstract: In one embodiment, a high-level compensation (HLC) module receives samples of an input signal and determines whether a magnitude of each sample, represented in a linear domain, is relatively low or relatively high by comparing the magnitude to a threshold. If a sample is less than or equal to the threshold, then it is considered to have a relatively low magnitude and the sample is not attenuated. If a sample is greater than the threshold, then it is considered to have a relatively high magnitude and the HLC module attenuates the sample according to a “soft” non-linear function. The “soft” non-linear function is characterized by at least two of the following characteristics: the non-linear function (i) increases monotonically, (ii) forms a convex upwards curve, (iii) has a first derivative at the threshold equal to one, and (iv) has a first derivative at a maximum possible magnitude value equal to zero.

Abstract: A method for merging a source electronic memory storage cluster into a destination electronic memory storage cluster may include designating a source storage cluster having a first configuration; designating a destination storage cluster having a second configuration; receiving a configuration database including mapping information associated with the first configuration of the source storage cluster; merging the configuration database for the source storage cluster into the destination storage cluster; identifying a conflict between the source storage cluster configuration and the destination storage cluster configuration by comparing mapping information for the imported configuration database for the source storage cluster to mapping information for a configuration database associated with the second configuration of the destination storage cluster; resolving the identified conflict between the source storage cluster configuration and the destination storage cluster configuration; and merging the configurat

Abstract: The present invention is a device for detecting short burst errors. The device includes a first signal input, wherein the first signal input is configured to receive a first signal. The device includes a second signal input, wherein the second signal input is configured to receive a second signal. The device includes a logic gate, wherein the logic gat is operable for receiving the first signal vial the first signal input, receiving the second signal via the second signal input, and generating a logic output gate signal based on the received first signal and the second signal. Furthermore, the device includes a filter, wherein the filter is configured for receiving the logic output gate signal from the logic gate and generates a filter output signal based upon the received logic output gate signal, wherein the filter output signal is operable for flagging errors.

Abstract: A RAID system is provided in which, in the event that a rebuild is to be performed for one of the PDs, a filter driver of the operating system of the computer of the RAID system informs the RAID controller of the RAID system of addresses in the virtual memory that are unused. Unused virtual memory addresses are those which have never been written by the OS as well as those which have been written by the OS and subsequently freed by the OS. The RAID controller translates the unused virtual memory addresses into unused physical addresses. The RAID controller then reconstructs data and parity only for the unused physical addresses in the PD for which the rebuild is being performed. This reduces the amount of data and parity that are rebuilt during a rebuild process and reduces the amount of time that is required to perform the rebuild process. In addition, the RAID system is capable of being configured to prevent or reduce data sprawl.

Abstract: An electronic device comprising a bond pad on a substrate and a wire bonded to the bond pad.

Abstract: An apparatus and a method for implementing transmitter compliance transfer functions in software are disclosed. As per the present invention, a transfer function model is provided to modify the real time signal received from a device, such as a transmitter, to be analyzed. The real-time signal is modified according to a relative s-parameter(s) or transfer function, and is provided to a display device, such as an oscilloscope, in order to analyze the modified signal. In one embodiment, the invention may be software integrated within an oscilloscope or in a computer system.

Abstract: A random number generator includes a ring oscillator having an EX-OR gate and four inverters together forming a loop. This loop enters stable state for a start signal having the low level and oscillates for the start signal having the high level. When the start signal has a pulse of a width shorter than the loop's delay time, output nodes responsively, sequentially enter metastable state hovering between the high and low levels. The metastable waveform becomes smaller with time and finally disappears. As metastable state cannot be controlled in longevity, it disappears at any random number node. A counter thus outputs a signal serving as true random number data depending on the longevity of the metastable state. A random number generator miniaturized and having reduced power consumption, and of high performance can thus be implemented.

Abstract: Disclosed is a method for reducing latency between two clock domains in a digital electronic device. The time between a write to a queue position and a corresponding read of the queue position is reduced by up to one clock cycle by including a delay in the time before first writing data to a First In First Out (FIFO) queue used to buffer and synchronize data between two clock domains. The two clock domains have the same frequency, but may be out of phase. Reducing the latency between the write and the corresponding read reduces the required size of the FIFO queue and also results in more efficient system operation.

Abstract: An apparatus having a memory module and an initialization module is disclosed. The initialization module may be configured to (i) mark a particular location in the memory module as an uninitialized location by writing a predetermined word into the particular location in response to an occurrence of an event, (ii) read a read word from an address in the memory module in response to a read cycle and (iii) generate an interrupt signal by analyzing the read word, the interrupt signal being asserted where the read word indicates that the address is the uninitialized location in the memory module.

Abstract: Disclosed is a method that simultaneously transfers DMA data from a peripheral device to a hardware assist function and processor memory. A first DMA transfer is configured to transfer data from the peripheral to a peripheral DMA engine. While receiving the data, the DMA engine simultaneously transfers this data to processor memory. The DMA engine also transfers a copy of the data to a hardware assist function. The DMA engine may also simultaneously transfer data from processor memory to a peripheral device while transferring a copy to a hardware assist function.

Abstract: Embodiments of the invention include a semiconductor integrated circuit package that includes a substrate having an integrated circuit die attached thereto. The package includes a ESD shield attached to the substrate. The ESD shield configured to increase the ESD hardness of the package. The ESD shield can further serve to stiffen the package to prevent warping and operate as a heat spreader.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, some embodiments of the present invention provide data processing circuits including a pattern detection circuit having at least two data detector circuits each operable to receive the same series of data samples and to provide a first detected data output and a second detected data output, respectively. In addition, the data pattern detection circuit includes a result combining circuit that is operable to assert a pattern found output based at least in part on the first detected data output and the second detected data output.

Abstract: Methods and apparatuses for correcting an error in a data stream that is coded with a line code and an error detection scheme. Information relating to the line code is used to locate at least one possible error character. At least one possible correct character to replace one or more of the at least one possible error character is then identified. Subsequently, the error detection scheme is applied to the data stream updated with one of the at least one possible correct character. If none of the at least one possible correct character results in a valid data stream, an error that is observable by a user is generated.

Abstract: A first physical capacity of a first physical storage device is determined. A second physical capacity of a second physical storage device that has a physical capacity greater than the first physical capacity is determined. A storage space pool comprising at least a first logical drive, a second logical drive, and a third logical drive is created. The first logical drive corresponds to the first storage device and has the same capacity as the first physical capacity. The second logical drive corresponds to a first portion of the second storage device. The third logical drive corresponds to a second portion of the second storage device. The first portion and the second portion having at least the first physical capacity. Thus, two portions having at least the first physical capacity are utilized on the second physical drive instead of just one portion.

Abstract: Methods and apparatus for expanded capacity virtual volumes in a virtualized storage system. A storage controller of the storage system parses a SCSI command block as it is received to generate a tag value indicating a segment of a virtual volume to which the command block is directed. The tag value is used to select one of a plurality of mapping segment objects stored in a memory of the controller. Each mapping segment objects maps logical block addresses of a corresponding segment of a corresponding virtual volume to physical storage addresses on the physical storage devices that comprise the virtual volume. An I/O processing circuit of the controller then processes the SCSI command block in accordance with the mapping information in the selected mapping segment object. In one exemplary embodiment, each segment of a virtual volume comprises 2 terabytes of storage capacity of the virtual volume.

Abstract: A method for training an electronic memory may include receiving a first delay value and a second delay value. The first delay value and the second delay value may be associated with a first data strobe indicating when to sample data on a first memory lane of the electronic memory. The method may also include determining a difference between the first delay value and the second delay value. The method may further include receiving a third delay value associated with a second data strobe indicating when to sample data on a second memory lane of the electronic memory. The method may also include determining a fourth delay value for the second memory lane of the electronic memory utilizing the third delay value and the determined difference between the first delay value and the second delay value.

Abstract: A method of automatic luminance-chrominance delay compensation is disclosed. The method generally includes the steps of (A) generating an intermediate signal by processing a video signal such as to enhance a plurality of edges in a picture within the video signal, the picture having a luminance component and a chrominance component temporally separated from each other by an actual delay, (B) identifying an estimated delay between the luminance component and the chrominance component by correlating the luminance component in the intermediate signal to the chrominance component in the intermediate signal at a plurality of relative delays and (C) compensating for the actual delay by delaying one of either (i) the luminance component and (ii) the chrominance component by the estimated delay.