Abstract: Disclosed is a charging apparatus to supply a power to a battery of an electric vehicle. The charging apparatus includes a bidirectional power conversion unit including three pairs of switching device groups and having one end connected to a power system and an opposite end; an energy storage unit connected to the opposite end of the bidirectional power conversion unit to store the DC power output through the opposite end of the bidirectional power conversion unit; a multi-DC power output unit to output the DC power to an outside in the first inverse operation mode; and a charging control unit to detect a charging condition of the charging apparatus. The switching device groups serve as buck-converters, respectively, in the first inverse operation mode to convert the DC power into another DC power having a level different from a level of the DC power.

Abstract: Operations of an electronic device are simulated by generating and executing a bit-accurate model of the device using an input signal having at least one transition that corresponds to a step input having a pre-transition value (e.g., 0 for a positive transition) for a specified duration before the transition and a post-transition value (e.g., 1 for a positive transition) for a specified duration after the transition. The corresponding step-response results are differentiated with respect to time to generate impulse-response results for the device. The impulse-response results are converted into the frequency domain to determine frequency-domain characteristics of the device that are used to generate a statistical model of the device, which can be executed to simulate all operations of the device, include low bit-error-rate (BER) simulations that would take too long to simulate using the bit-accurate model.

Abstract: An apparatus includes a first circuit and a second circuit. The first circuit may be configured to receive a signal, where low frequency content of the signal is attenuated due to high pass filtering by a medium carrying the signal and a coupling. The second circuit may be configured to automatically set a gain of a baseline wander correction loop to restore the low frequency content in the signal based upon a sample taken from a first point in a signal pathway of the first circuit.

Abstract: Various embodiments of the present invention provide systems and methods for data writing. As an example, a heat assisted loopback circuit is discussed that includes: a read circuit, a magnetic write circuit, a heat write circuit, and a loopback circuit. The read circuit is operable to sense data from a storage medium, and to provide the sensed data as a read output. The magnetic write circuit is operable to provide a write output corresponding to an excitation signal of a write head. The heat write circuit is operable to provide a heat output corresponding to an excitation signal of a heat source. The loopback circuit is operable to selectively couple a derivative of the heat output to the read output and to selectively couple a derivative of the write output to the read output.

Abstract: A bracket is fitted over an external connector that has fingers, such as EMI fingers, that are spring loaded and provide electrical connections between outside panels and the main enclosure of a device. The bracket depresses the EMI fingers and provides ease of removal. A tool is dimensioned so that a user has room to grip it while not interfering with a bracket, such as a PCI bracket, when in use. The tool is dimensioned so that it can be slid over a bracket so as to compress the fingers, such as EMI fingers, and the bracket can be removed without damaging the connector. A cut out may be offset from the center to provide additional surface to grip by a user.

Abstract: A packet-router architecture in which buffer modules are interconnected by one or more interconnect fabrics and arranged to form a plurality of hierarchical buffer levels, with each higher buffer level having more buffer modules than a corresponding lower buffer level. An interconnect fabric is configured to connect three or more respective buffer modules, with one of these buffer modules belonging to one buffer level and the other two or more buffer modules belonging to a next higher buffer level. A buffer module is configured to implement a packet queue that (i) enqueues received packets at the end of the queue in the order of their arrival to the buffer module, (ii) dequeues packets from the head of the queue, and (iii) advances packets toward the head of the queue when the buffer module transmits one or more packets to the higher buffer level or to a respective set of output ports connected to the buffer module.

Abstract: A bus interconnect for interconnecting one or more master devices with one or more slave devices in a system includes at least one slave interface module adapted for communicating with a corresponding one of the master devices and at least one master interface module adapted for communicating with a corresponding one of the slave devices. The bus interconnect further includes a configurable response module coupled with the slave interface module. The configurable response module is operative to generate different configurable responses associated with access requests to corresponding portions of an address space of the system.

Abstract: A dual rail memory operable at a first voltage and a second voltage includes an input circuit, an output circuit and a clock generator circuit coupled with the input circuit. The input circuit is operable to receive at least a first input signal referenced to the first voltage and to generate a second input signal referenced to the second voltage. The output circuit is operable to receive at least a first output signal referenced to the second voltage and to generate a second output signal referenced to the first voltage. The clock generator circuit is operable to receive a first clock signal referenced to the first voltage and to generate a second clock signal referenced to the second voltage, a logic state of the second clock signal being a function of a logic state of the first clock signal.

Abstract: A system and method for servers to belong to a cascaded cluster of nodes (or servers) is disclosed. Servers share storage in common without the need of an external element such as a switch and or external storage device. SAS technology is used with direct attached drives in each node, and connections between each node, to emulate a SAN environment through a cascaded SAS topology. SAS HBAs each containing an SAS expander, connect elements internal to each server with elements external to each. This cascaded DAS clustering enables bi-directional traffic from each server in the cluster to all other servers and their attached drives.

Abstract: A reference circuit comprises a first proportional to temperature component providing a first quantity exhibiting a first type of variation as a function of temperature, a first complementary to temperature component providing a second quantity exhibiting a second type of variation as a function of temperature that is complementary to the first type of variation, and curvature correction circuitry. An output of the reference circuit provides a reference signal generated based on a combination of the first and second quantities. The curvature correction circuitry is coupled to the reference circuit output and comprises at least one additional complementary to temperature component. The curvature correction circuitry adjusts the reference signal in a feedback arrangement to compensate for a temperature response bowing effect attributable to combining the first and second quantities. The reference circuit may be implemented in a disk-based storage device for use in fly height control or other control functions.

Abstract: A method of generating length parameters, comprising the steps of reading a data stream from a host, detecting a particular field of the data stream, and calculating a variable based on a length parameter of a first list to be transferred. The data stream may comprise a plurality of definitions. The method may also comprise the step of selecting one of the list definitions. One of the list definitions may be used to generate a length parameter used in a second list in response to (i) the particular field of the data stream and (ii) the length parameter of the first list.

Abstract: A stitch area configuration for word gates and control gates of a twin MONOS metal bit array comprises control gates on sidewalls of the word gates wherein the word gates and control gates run in parallel. Control gate poly contacts contact each of the control gates aligned in a row at the stitch area perpendicular to the control gates. Two word gate poly contacts at the stitch area contact alternating word gates. Also provided are bit lines, word line and control gate decoders and drivers, a bit line decoder, a bit line control circuit, and a chip controller to control the memory array. The invention also provides twin MONOS metal bit array operations comprising several control gates driven by one control gate driver circuit and one word gate driven by one word gate driver circuit, as well as erase inhibit and block erase.

Abstract: Systems, methods, devices, circuits for data processing, and more particularly, and more particularly to data processing relying on efficiency improved data detection.

Abstract: Methods and apparatus are provided for programming multiple program values per signal level in flash memories. A flash memory device having a plurality of program values is programmed by programming the flash memory device for a given signal level, wherein the programming step comprises a programming phase and a plurality of verify phases. In another variation, a flash memory device having a plurality of program values is programmed, and the programming step comprises a programming phase and a plurality of verify phases, wherein at least one signal level comprises a plurality of the program values. The signal levels or the program values (or both) can be represented using one or more of a voltage, a current and a resistance.

Abstract: Methods and structure are provided for enhancing zone configuration processes in a Serial Attached SCSI (SAS) architecture. The method includes embedding, at a SAS initiator, a ZONE UNLOCK request within a Serial Management Protocol (SMP) ZONE ACTIVATE command. The method also comprises transmitting the SMP ZONE ACTIVATE command to a SAS expander, and receiving, at the SAS expander, the SMP ZONE ACTIVATE command. Further, the method includes detecting, at the SAS expander, the ZONE UNLOCK request within the SMP ZONE ACTIVATE COMMAND. Additionally, the method includes copying, at the SAS expander, shadow SAS zoning data from a memory of the expander to current SAS zoning data at the memory of the expander responsive to acquiring the SMP ZONE ACTIVATE command. The method also comprises unlocking the SAS expander responsive to extracting the ZONE UNLOCK request from the SMP ZONE ACTIVATE command.

Abstract: In one embodiment, a simulator, e.g., for a hard-disk drive selects for testing a signal-to-noise ratio (SNR) value from a range of ratios and an error-correction codeword pattern from a range of codeword patterns. The simulator simulates a communications channel by applying write noise, inter-symbol interference, and read noise to the codeword pattern to generate a noisy signal. In addition, the simulator adds arbitrary-noise to the codeword to accelerate the speed of the simulation. The arbitrary noise increases the probability of converging on a trapping set and does not represent any noise introduced by the communications channel. The simulator attempts to decode the noisy signal, and if decoding is unsuccessful, then the simulator increments an error counter corresponding to the selected signal-to-noise ratio. This process is repeated for all possible combinations of signal-to-noise ratio values and codeword patterns to determine the error rate for all of the signal-to-noise ratio values.

Abstract: Disclosed is a method of detecting the disconnection state of a power cable in an inverter system. The method includes detecting a battery voltage, detecting a DC-link voltage, detecting the disconnection state of the power cable based on a difference value between the detected battery voltage and the DC-link voltage, and stopping driving of a motor if the power cable is detected as being disconnected.

Abstract: The present invention provides an HDD performance enhancement system that utilizes excess disk capacity as cache memory to enhance the I/O performance of the drive. The cache memory is distributed throughout the disk, for example in alternating tracks, sectors dedicated to serving as cache, or other distributed cache track segments or segment groups. Distributing the cache throughout the disk reduces the physical distance of the I/O head to the closest available cache location. The system minimizes the write seek time by storing write data in the closest available cache location. High utilization data blocks are stored in multiple cache location locations to reduce read seek time for high utilization data. The cached data is eventually written to permanent memory and cleared from the cache during idle or low data storage utilization periods.

Abstract: An apparatus comprises a clock generator, first and second memory drivers and a multiple-port memory device having at least first and second ports configured to receive input signals from and supply output signals to respective ones of the first and second memory drivers, the multiple-port memory device further comprising a single-port memory device and control circuitry coupled between the first and second ports and the single port of the single-port memory device. The clock generator generates first and second clock signals having respective first and second clock rates, the clock rate of the second clock signal being an integer multiple of the clock rate of the first clock signal. The first and second memory drivers are configured to operate using the first clock signal at the first clock rate, and the single-port memory device is configured to operate using the second clock signal at the second clock rate.

Abstract: Lighting systems, apparatus, and methods are disclosed, which employ optical transmission of two-dimensional control signals to manipulate lighting elements. The lighting apparatus can include a projector with an IR LED array to wirelessly transmit pixel information onto a target space. The pixel information controls lighting elements within the target space. The two-dimensional control signals can includes subareas corresponding to lighting elements in a control array. The lighting elements can be lights producing light of desired wavelengths including infrared and/or visible wavelengths. LEDs can be used as light sources in exemplary embodiments.