Abstract: A computer-aided design method for developing, simulating, and testing a read-channel architecture to be implemented in a VLSI circuit. The method uses a coset operating mode and nonzero-syndrome-based decoding to accelerate the simulation of the read-channel's error-rate characteristics corresponding to different parity-check matrices employed in the read-channel's turbo-decoder, such as a low-density parity-check decoder. The acceleration is achieved through recycling some previously generated log-likelihood-ratio values, which enables the method to sometimes bypass certain time-consuming processing steps therein.

Abstract: A method for estimating error probability of LDPC codes includes ordering LDPC codes according to features in each code with known error characteristics. The method includes identifying features in each LDPC code having known error characteristics; adding each code to one or more categories based on the existence of such features; and ranking the LDPC codes according to the level of error risk.

Abstract: A remote inspection system and a communication method thereof are provided. According to exemplary embodiments, the system may be implemented such that desired inspection data can be received from a meter only after unlocking the meter, by setting the meter to a lock state using an inherent obis code at the beginning and receiving a corresponding unlock obis code from a remote inspection server. This may result in further enhancement of security levels of the meter and the system.

Abstract: Methods and structure are disclosed for analyzing different signaling pathways through a test signal selection hierarchy utilizing test patterns. One embodiment comprises an integrated circuit that includes a block of circuitry, a test signal generator, and a test signal selection hierarchy. The block of circuitry generates internal operational (TOP) signals for performing functions. The test signal generator generates test patterns that correspond with the IOP signals. The test signal selection hierarchy receives IOP signals and the test patterns, and selectively routes received signals to test pads. The test signal selection hierarchy routes the test patterns via signaling pathways through the test signal selection hierarchy to provide outputs signals on the test pads. The output signals are usable by an external test system to determine two or more of: a crosstalk, inter-symbol interference, a signal skew, and a threshold voltage for detecting bit transition on signaling pathways.

Abstract: A device includes non-volatile memory and a controller. The controller receives a write request including data and a logical address associated with a file. The controller stores the data at a data storage segment having a physical address and associates the physical address with the logical address and a file identifier for the file. The controller receives a second write request including data and the logical address associated with the file. The controller stores the data at a second data storage segment having a second physical address and associates the second physical address with the logical address and the file identifier. When a file delete request for the file is received, the controller identifies the first physical address and the second physical address using the file identifier and erases the information stored at the first data storage segment and the second data storage segment based upon the file identification.

Abstract: Methods and structure are disclosed for normalizing storage performance across a plurality of logical volumes. One embodiment is a storage controller. The storage controller is adapted to couple with a plurality of host systems and a storage device. The storage controller is adapted to receive one or more requests to create logical volumes for the plurality of hose systems, and adapted to identify a plurality of performance zones for storage areas of the storage device. The performance zones exhibit different performance criteria for one or more of: reading data from the storage device and writing data to the storage device. The storage controller is further adapted to allocate storage from each of the plurality of performance zones for each of the plurality of logical volumes such that the performance criteria for accessing the storage device is distributed substantially uniformly across the plurality of logical volumes.

Abstract: A hard disk drive or other disk-based storage device comprises a storage disk, a read/write head configured to read data from and write data to the storage disk, and control circuitry coupled to the read/write head and configured to process data received from and supplied to the read/write head and to control positioning of the read/write head relative to the storage disk. The control circuitry is further configured to adjust at least one parameter of a write signal for a target bit to be written to the storage disk based on respective magnetization polarities of one or more adjacent bits previously written to the storage disk.

Abstract: A data processing system comprises data processing circuitry, a cache memory, and memory access circuitry. The memory access circuitry is operative to assign a memory address region to be allocated in the cache memory with a predefined initialization value. Subsequently, a portion of the cache memory is allocated to the assigned memory address region only after the data processing circuitry first attempts to perform a memory access on a memory address within the assigned memory address region. The allocated portion of the cache memory is then initialized with the predefined initialization value.

Abstract: An apparatus having a first memory and a circuit is disclosed. The first memory may be configured to store a plurality of timers. Each of the timers may have a respective value that indicates an expiration time. A first one of the timers nearest to expiring is generally stored at a first address of the first memory. The circuit may be configured to (i) assert a signal in response to the respective value of the first timer matching a counter of time, (ii) read a second of the timers and a third of the timers both from a second address of the first memory, (iii) sort the second timer and the third timer to determine which expires next and (iv) replace the first timer by writing one of the second timer or the third timer that expires next into the first memory at the first address.

Abstract: Disclosed is a cipher independent cryptographic hardware service. Cipher independent transactions are received into input slots (202). The input slots contain FIFOs to hold the transactions. The transactions are converted from cipher independent form to cipher dependent form (206) and timing as they are removed from the FIFOs. After cryptographic processing by cipher specific hardware, the results are sent to output FIFOs (212). Multiple FIFOs and cryptographic hardware may be used so that multiple cryptographic functions may be performed in parallel and simultaneously.

Abstract: A scan cell is configured to receive first, second and third data bits at respective first, second and third data inputs. A control input is configured to receive a control signal. Latching logic is configured to latch data received at the first and second latch inputs to a scan cell output. The first latch input is configured to receive the first data bit. Selection logic is configured to select between the second and third data bits depending on a state of the control signal, and to provide the selected bit to the second latch input.

Abstract: A device and method wherein a thermo electric generator device is disposed between stacks of a multiple level device, or is provided on or under a die of a package and is conductively connected to the package. The thermo electric generator device is configured to generate a voltage by converting heat into electric power. The voltage which is generated by the thermo electric generator can be recycled back into the die itself, or to a higher-level unit in the system, even to a cooling fan.

Abstract: A method and apparatus for closing a punctured blood vessel is described. The apparatus includes a suturing instrument adapted to apply at least one suture to at least a portion of a blood vessel in order to close a puncture wound therein. In a preferred embodiment, the suture is secured by crimping a sleeve member over the free ends of the suture with a crimping instrument.

Abstract: Various embodiments of the present invention provide methods and apparatuses for multi-level layer decoding of non-binary LDPC codes. For example, an apparatus is disclosed for layer decoding of multi-level low density parity check encoded data. The apparatus includes a low density parity check decoder operable to perform layered decoding of a plurality of circulant submatrices from an H matrix. The apparatus also includes a parity check calculator connected to the low density parity check decoder, operable to detect whether a stopping criterion has been met in the low density parity check decoder. The low density parity check decoder is also operable to end a decoding operation at less than a maximum number of iterations when the stopping criterion is met.

Abstract: Higher-level redundancy information computation enables a Solid-State Disk (SSD)controller to provide higher-level redundancy capabilities to maintain reliable operation in a context of failures of non-volatile (e.g. flash) memory elements during operation of an SSD. A first portion of higher-level redundancy information is computed using parity coding via an XOR of all pages in a portion of data to be protected by the higher-level redundancy information. A second portion of the higher-level redundancy information is computed using a weighted-sum technique, each page in the portion being assigned a unique non-zero “index” as a weight when computing the weighted-sum. Arithmetic is performed over a finite field (such as a Galois Field). The portions of the higher-level redundancy information are computable in any order, such as an order based on order of read operation completion of non-volatile memory elements.

Abstract: A method for back-off retry with priority routing in a single, cohesive SAS expander includes routing a data transfer between an input of a single, cohesive SAS expander and an output of the single, cohesive SAS expander, wherein the single, cohesive expander includes a first SAS expander, and at least one additional SAS expander via at least one inter-expander link (IEL). The routing of data may further include routing a first OPEN request on a direct path through the first SAS expander to a port of a device and routing a second OPEN request on an alternate path from the first SAS expander and through a second SAS expander to the port of the device. The method further includes determining link availability between the second SAS expander and the port of the device, and, upon determination of a failed link or a busy link, re-routing the data transfer from the second SAS expander to the first SAS expander or a third SAS expander, or retrying the data transfer through the second SAS expander.

Abstract: A method for transcoding from an MPEG-2 format to a VC-1 format is disclosed. The method generally comprises the steps of (A) decoding an input video stream in the MPEG-2 format to generate a picture; (B) determining a mode indicator for the picture; and (C) coding the picture into an output video stream in the VC-1 format using one of (i) a VC-1 field mode coding and (ii) a VC-1 frame mode coding as determined from the mode indicator.

Abstract: The present disclosure is directed to a method for communication between an initiator system and a block storage cluster. The method may comprise initiating an input/output (I/O) request from the initiator system to a first storage system included in a plurality of storage systems of the block storage cluster, each of the plurality of storage systems comprising a plurality of data segments; receiving a referral response from the first storage system, the referral response providing information describing a layout of data requested in the I/O request; obtaining a virtual disk count, a segment size, and at least one indexed port identifier based on the referral response; and directing the I/O request from the initiator system to the block storage cluster based on the virtual disk count, the segment size, and the at least one indexed port identifier.

Abstract: Disclosed herein is a contact apparatus for a circuit breaker, and the circuit breaker may include a stationary electrode portion having a stationary contact; and a movable electrode portion configured to be brought into contact with and separated from the stationary electrode portion, wherein the movable electrode portion includes a movable conductor portion configured to be approached to and spaced from the stationary electrode portion; and a movable contact combined with the movable conductor portion in a relatively movable manner to be brought into contact with and separated from the stationary contact. Through this, it may be possible to alleviate a shock when contacting a contact.

Abstract: Methods and structure for transferring administrative information through a communication interface. Features and aspects hereof provide for exchanging administrative information between an initiator device and a target device using read and write commands encoded with a reserved sub-tag value. In the context of a Serial Advanced Technology Attachment (SATA) system, a portion of a parameter (e.g., the LBA parameter) of a read or write command (a Native Command Queuing command) is defined to encode a sub-tag value. One or more sub-tag values are reserved to indicate that the corresponding read or write command is related to the exchange of administrative information rather than the reading or writing of data on a storage device. A parameter value encoded in the LBA field or data length field of the read or write command indicates administrative data to be returned to the initiator or to be updated within the target device.