Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for power governance in a data processing system.

Abstract: Various embodiments of the present invention provide systems and methods for detecting contact. For example, a method for detecting head contact is disclosed that includes: receiving an interface signal operable to indicate a physical contact between a sensing device and a storage medium; band pass filtering a data set derived from the interface signal to yield a band pass filtered output; comparing the band pass filtered output to a level threshold to yield a comparator output; summing the comparator output with at least one prior instance of the comparator output to yield an aggregated value; and comparing the aggregated value to an aggregate threshold to yield a contact output.

Abstract: Described embodiments provide for detection and selection by the user of a ticker region within a first video broadcast; and copying and overlaying the detected and selected ticker region over a second video broadcast. Motion estimation techniques are employed to identify the ticker region location and associated borders of the ticker region. The streaming video corresponding to the ticker region is buffered. Some embodiments allow for post-processing of the overlayed ticker region to, for example, eliminate artifacts of, match resolution to, and match aspect ratio of the overlayed ticker region to the second video broadcast.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is discussed that includes: a buffer circuit, an equalizer circuit, a data processing circuit, and a retry determination circuit. The buffer is operable to store digital samples as a buffered output, and the equalizer circuit is operable to equalize the buffered output using a first equalization target to yield a first equalized output, and to yield a second equalized output using a second equalization target. The retry determination circuit is operable to select the second equalization target based at least in part on an occurrence of an error.

Abstract: A method and/or a system of unified management of a hardware interface framework is disclosed. In one embodiment, a method of the hardware interface framework includes applying to a client interface module with a generic agent module agnostic to a change in a device coupled to the hardware interface framework and a change in a management module and communicating a management data of the management module between the client interface module and a server interface module coupled to the device using the generic agent module. The method may also include synchronously communicating a request data of the management module to collect a response data of the device and asynchronously communicating an event data of an adapter module to the management module.

Abstract: Provided is an electronic component box for a vehicle. The electronic component box for a vehicle, the electronic component box including a housing formed of a plastic material and manufactured through plastic injection molding, the housing having an opened top surface, a top cover formed of a plastic material and manufactured through the plastic injection molding, the top cover covering the opened top surface of the housing, a base cover seated on a bottom surface of the housing, an electronic component set seated on a top surface of the base cover, and a plated layer disposed on an inner circumferential surface of the housing and a back surface of the top cover to shield an electromagnetic wave.

Abstract: Various embodiments of the present invention provide systems and methods for data filter tuning. As an example, a method for filter tuning is disclosed that includes: providing a tunable filter having an operation filter and a calibration filter; applying a low frequency test input to the operation filter in place of an input signal to yield a first filter output; calculating a low frequency magnitude value corresponding to the first filter output; applying a high frequency test input to the operation filter in place of an input signal to yield a second filter output; calculating a high frequency magnitude value corresponding to the second filter output; modifying a tuning factor of the calibration filter when a ratio of the high frequency magnitude value and the low frequency magnitude value is outside of a defined range; and storing the tuning factor of the calibration filter when the ratio of the high frequency magnitude value and the low frequency magnitude value is within the defined range.

Abstract: An apparatus comprising an initiator circuit and a target circuit. The initiator circuit may be configured to (i) communicate with a network through a first interface and (ii) generate testing sequences to be sent to the network. The target circuit may be configured to (i) receive the testing sequences from the network through a second network interface and (ii) respond to the testing sequences.

Abstract: Provided is an electronic component box for a vehicle. The electronic component box for a vehicle, the electronic component box including a housing formed of a plastic material and manufactured through plastic injection molding, the housing having an opened top surface, a top cover formed of a plastic material and manufactured through the plastic injection molding, the top cover covering the opened top surface of the housing, a base cover seated on a bottom surface of the housing, an electronic component set seated on a top surface of the base cover, and an inner cover accommodated within the housing, the inner cover covering the electronic component set to shield an electromagnetic wave emitted from the electronic component set.

Abstract: A hard disk drive or other disk-based storage device comprises a storage disk, a read/write head configured to read data from and write data to the disk, and control circuitry coupled to the read/write head and configured to process data received from and supplied to the read/write head. The control circuitry comprises calibration circuitry configured to vary a phase of a clock signal as a test pattern is written to the storage disk as part of a calibration procedure, and disk locked clock circuitry coupled to the calibration circuitry and configured to obtain phase lock between the clock signal and a timing pattern on a surface of the storage disk. The calibration circuitry is further configured to determine an initial phase update value to be applied by the disk locked clock circuitry in a control loop as the phase of the clock signal is varied as part of the calibration procedure.

Abstract: Various embodiments of the present invention provide apparatuses, systems and methods for data detection in a detector with a pruning control system. For example, a data detector is disclosed that includes a first set of counters operable to distinguish prunable data from non-prunable data in the data detector, a second set of counters operable to generate initial values for the first set of counters, and a prune control signal generator operable to generate a prune control signal based on the first set of counters. The second set of counters is operable to generate the initial values at least in part before a syncmark is detected in a data sector. The initial values are used to initialize the first set of counters when the syncmark is detected in the data sector. The prune control signal controls whether the data detector is allowed to prune a trellis.

Abstract: A memory device includes a memory array comprising a plurality of memory cells. At least a given one of the memory cells comprises a pair of cross-coupled inverters and associated write assist circuitry. The write assist circuitry comprises first switching circuitry coupled between a supply node of a device of the first inverter and a supply node of the memory cell, and second switching circuitry coupled between a supply node of a device of the second inverter and the supply node of the memory cell. The first and second switching circuitry are separately controlled, with the first switching circuitry being controlled using a wordline and an uncomplemented bitline of the memory device, and the second switching circuitry being controlled using the wordline and a complemented bitline of the memory device.

Abstract: A system and device for reducing instantaneous voltage droop (IVD) during a scan shift operation. In one embodiment, a system includes a first group of clock gating cells configured to receive an input clock signal and a first group of flip-flops coupled to the first group of clock gating cells. Each clock gating cell of the first group of clock gating cells includes a first delay element to delay the input clock signal by a first duration during a scan shift operation. The system also includes a second group of clock gating cells configured to receive the input clock signal, and a second group of flip-flops coupled to the second group of clock gating cells. Each clock gating cell of the second group of clock gating cells includes a second delay element to delay the input clock signal by a second duration during the scan shift operation.

Abstract: A method for dynamic storage tiering may include, but is not limited to: receiving an input/output (I/O) request from a host device; determining whether the I/O request results in a cache hit; and relocating data associated with the I/O request between a higher-performance storage device and lower-performance storage device according to the determination whether the data associated with the I/O request is stored in a cache.

Abstract: Methods and systems for reducing the signal path count between circuits within a SAS expander used for establishing SAS connections. The system comprises a SAS expander. The SAS expander comprises a plurality of link layer control circuits, each link layer control circuit adapted to communicatively couple with a SAS device. The SAS expander further comprises a connection manager communicatively coupled with the link layer control circuits for routing communications between the link layer control circuits. Each of the plurality of link layer control circuits is adapted to establish a SAS connection with another link layer control circuit through the connection manager by segmenting a plurality of interconnect signals into multiple data segments for sequential transmission to the connection manager, (e.g., without impacting the performance of the connection manager). The connection manager interprets the data segments to extract the plurality of interconnect signals to establish the SAS connection.

Abstract: The present inventions are related to systems and methods for transferring information to and from a storage medium, and more particularly to systems and methods for positioning a sensor in relation to a storage medium. For example, an apparatus for determining a sensor position is disclosed that includes discrete Fourier transform calculators operable to process input data to yield a magnitude response of the input data at each of a number of candidate frequencies, a comparator operable to compare the magnitude responses to yield a winning candidate frequency, a servo controller operable to process at least one servo field in the input data to identify a position of a sensor based on the at least one servo field, and a servo frequency synthesizer operable to establish a frequency of operation in the servo controller based at least in part on the winning candidate frequency.

Abstract: Techniques are disclosed for performing branch metric computations/noise predictive calibration/adaptation for over-sampled Y samples. In one or more embodiments, the techniques employ a data processing apparatus (circuit) that includes a parallel to serial convertor configured to receive a first stream of sample data (e.g., Y samples) and a second stream of sample data (e.g., Z samples). The parallel to serial convertor is operable to combine the first stream of sample data and the second stream of sample data into a combined stream of sample data (e.g., combined Y and Z samples). The data processing apparatus (circuit) further includes a filter (e.g., a noise predictive finite impulse response (NPFIR) filter, a noise whitening filter, such as a noise predictive calibration/adaptation module (NPCAL) filter, and so forth) that is configured to receive the combined stream of sample data and whiten noise in the combined stream of sample data.

Abstract: A method of determining signal routing in an integrated circuit includes providing first coordinates of an input/output cell and second coordinates of an input/output pad to a parametric routing module. The parametric routing module receives at least one wire path parameter. The parametric routing module uses the at least one connection path parameter to determine a physical dimension of a wire path between the first coordinates and the second coordinates.

Abstract: An IC capacitor bank includes a plurality of high-k metal-insulator-metal (MIM) capacitors connected to a pair of conductive traces. A fusible trace located on an end of one of the pair of conductive traces forms a capacitor column connected between supply lines, such that failure of a dielectric in the MIM capacitors causes the fusible trace to at least partially open thereby limiting a fault current in the capacitor column. Additionally, a method of manufacturing an IC capacitor bank includes providing a plurality of high-k metal-insulator-metal (MIM) capacitors connected to a pair of conductive traces and locating a fusible trace on an end of the pair of conductive traces to form a capacitor column that is connected between supply lines, such that failure of a dielectric in the MIM capacitors causes the fusible trace to at least partially open thereby limiting a fault current in the capacitor column.

Abstract: The present disclosure relates to an apparatus for diagnosing a DC link capacitor. A DC voltage provided from a power supplier to a motor is controlled to have a predetermined level (or magnitude). When a voltage of the DC link reaches a predetermined voltage, the ratio of change of capacitance values of the DC link capacitor is estimated, by considering power consumption of a resistor of the motor (i.e., power consumption of a load), power consumption of the power supplier and a switching loss of an inverter part, and a deteriorated level of the DC link capacitor is diagnosed using the estimated ratio.