Abstract: An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises scan cells configured to form scan chains. At least a given one of the scan cells is a multiple scan input scan cell having at least first and second scan inputs. In a first scan shift mode of operation, the given scan cell is configured with a first plurality of other scan cells into a scan chain of a first type using the first scan input. In a second scan shift mode of operation, the given scan cell is configured with a second plurality of other scan cells different than the first plurality of other scan cells into a scan chain of a second type using the second scan input.

Abstract: An apparatus comprising a controller and an array. The controller may be configured to generate control signals in response to one or more input requests. The array may comprise a plurality of solid state devices. The solid state devices may be configured to (i) read and/or write data in response to the control signals received from the controller and (ii) distribute writes across the plurality of solid state devices such that each of said solid state devices has a similar number of writes.

Abstract: Described embodiments provide method of adapting pulse response taps of a receiver. An analog-to-digital converter (ADC) generates an ADC value for each bit sample of a received signal. An error signature analysis (ESA) module defines a window of bit samples and, for the window, estimates a bit value corresponding to each sample based on the ADC value. The ESA module generates (i) a reconstructed ADC value corresponding to an estimated cursor bit based on a number of pre-cursor estimated bits, the estimated cursor bit, and a number of post-cursor estimated bits, and (ii) an error signature value based on the reconstructed ADC value and the ADC value. Based on the error signature value and a minimum pulse response value, it is determined whether the cursor bit corresponds to residual inter-symbol interference (ISI), and, if so, the error signature value is accumulated and tap values for each pulse response tap are adapted.

Abstract: A method and/or system may be configured to receive an input/output (I/O) request from an initiator system, add priority information to a multiple path referral for each port on which data can be accessed, selectively omit ports on which data may be accessed, transmit the multiple path referral from the target to the initiator, and/or choose a path on the initiator with the highest performance.

Abstract: A system, method, and computer program product are provided for inserting a gap in information sent from a drive to a host device. In operation, one or more commands are received at a drive from a host device. Additionally, information is queued to send to the host device. Furthermore, a gap is inserted in the information to send to the host device such that the host device is capable of sending additional commands to the drive.

Abstract: A method of modifying software associated with network devices includes transmitting a modification message by a first network device in response to software associated with the first network device being modified; transmitting second software identification information by a second network device in response to receiving the modification message from the first network device; providing a database comprising the first product identifier, the second product identifier, first software identification information, and the second software identification information; and modifying software associated with the second network device using the database. The first network device is associated with a first product identifier, and the second network device is associated with a second product identifier. The second software identification information identifies software associated with the second network device, and the first software identification information identifies software associated with the first network device.

Abstract: Methods and systems for advanced interrupt processing and scheduling are provided. The system comprises a memory operable to store interrupt priorities, an interface, and a processor operable to acquire incoming interrupts and to handle the incoming interrupts according to the interrupt priorities. The processor is also operable to receive interrupt processing criteria from the interface (sent, for example, from a device not directly coupled with the system), and to modify the interrupt priorities of the memory based upon the interrupt processing criteria without losing incoming processing requests for the system. Additionally, the processor is operable to process the incoming interrupts according to the modified interrupt priorities responsive to modifying the interrupt priorities.

Abstract: Disclosed are an apparatus and a method for providing an image to provide real-time image data photographed by an image photographing apparatus. The apparatus includes a real-time image data receiving unit to receive the real-time image data; a real-time image data filtering unit to image-process the real-time image data; a real-time image data storing unit to store the real-time image data of a specific section from among the image-processed real-time image data; and a display unit to display the real-time image data.

Abstract: A high availability DAS system uses a solid state cache to provide near active-active performance in a DAS duster, while retaining the implementation simplicity of active-passive or dual active system. Each node in the duster may include a solid state cache that stores hot I/O in an active-active mode, which allows the data to be read from or written to the underlying dual-active or active/passive DAS RAID system only when access to the “hot Region” cools down or in the case of Cache Miss. The hot I/O data includes hot read data that accumulated dynamically regardless of ownership of the drives where the hot read data is permanently stored. The hot I/O data also includes hot write data that is mirrored across the solid state cache memories to avoid potential dirty write data conflicts and also to provide High Availability in case of server failures.

Abstract: A driver circuit configured to generate a drive signal for an optical source comprises an overshoot controller that provides an amount of overshoot for a given logic state of the drive signal as a function of a duration of at least one previous logic state of the drive signal. The drive signal may alternate between a first logic state associated with a first operating mode of the optical source and a second logic state associated with a second operating mode of the optical source. The overshoot controller may be configured to provide amounts of overshoot for respective instances of the first logic state that are proportional to the durations of their respective immediately preceding second logic states. The driver circuit may be implemented in a heat-assisted magnetic recording system in which the optical source alternates between on and off states associated with respective magnetic write and magnetic read modes.

Abstract: The present disclosure includes methods and systems that share memory located on one PCIe based HBA across other PCIe based HBAs in the system. In addition, the backup battery is effectively shared across multiple PCIe based HBAs in the system. This approach saves significant costs by avoiding the need to have a separate DRAM with its own dedicated battery backup on each HBA board in the system. This also allows the redundant memory and backup batteries to be removed while still retaining the same functionality through the common DDR3 memory chip and battery backup shared across multiple HBAs in the system. The component cost for batteries and memory, management module, board space, and the board manufacturing cost are all reduced as a result.

Abstract: A hierarchical design flow generator for designing integrated circuits is disclosed. In one embodiment, the hierarchical design flow generator includes: (1) a partitioner configured to partition a hierarchical design flow for designing an IC into a late design flow portion and an early design flow portion, (2) a timing budgeter configured to provide a timing budget for the IC design based on initial timing constraints and progressive time constraints generated from the late design flow portion and the early design flow portion and (3) a modeler configured to develop a model for a top level implementation of the IC design based on the timing budget and block implementations generated during the late design flow portion.

Abstract: The invention may be embodied in a multiple-disk data storage system including a controller module that initiates an optimization algorithm to set maximum queue depth of each disk of the data storage system to desired queue depth of each disk. Desired queue depth of each disk may be associated with performance factors including, but not limited to, input/output operations per second (IOPs), average response time, and/or maximum response time of each disk. Desired queue depth of each disk may be further associated with priority rankings of performance factors.

Abstract: An apparatus generally including a first circuit and a second circuit is disclosed. The first circuit may be configured to generate an intermediate bitstream by parsing a Joint Picture Expert Group (JPEG) bitstream carrying a picture. The intermediate bitstream generally includes one or more encoded frames each representing a portion of the picture. The second circuit may be configured to (i) generate one or more intermediate images by decoding the encoded frames and (ii) recreate the picture using the intermediate images.

Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for data encoding.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes a media defect detector circuit. The media defect detector circuit is operable to compare a data input derived from a medium against at least a first defect level to yield a first level output, and a second defect level to yield a second level output; and provide a combination of the first level output and the second level output as a defect quality output. A value of the defect quality output corresponds to a likelihood of a defect of the medium.

Abstract: An apparatus comprising an inter symbol interference (ISI) cancellation circuit and a detector circuit. The inter symbol interference (ISI) cancellation circuit may be configured to minimize ISI at data sampling and crossing sampling points in a symbol interval of an input signal. The detector circuit may be configured to generate data samples and crossing samples at the data sampling and crossing sampling points in the symbol interval of the input signal.

Abstract: An apparatus having a first circuit and a second circuit. The first circuit may be configured to generate an output signal in response to (i) an intermediate signal, and (ii) a clock signal. The second circuit may be configured to generate the intermediate signal and a digital complement of the output signal in response to (i) an input signal and (ii) the clock signal. The intermediate signal may form a feedback to ensure the output signal and the digital complement of the output signal are in complementary states during a power up.

Abstract: A driver circuit for a laser diode or other optical source comprises a controllable termination for a transmission line coupled between the driver circuit and the optical source, with the controllable termination being switchable between at least first and second termination configurations. The transmission line comprises a first conductor coupled to a first terminal of the optical source and a second conductor coupled to a second terminal of the optical source, and the driver circuit comprises a first current source configured to drive the first conductor, and a second current source configured to drive the second conductor. By way of example, the first termination configuration may comprise an alternating current (AC) termination configuration and the second termination configuration may comprise a direct current (DC) termination configuration.