Abstract: In one embodiment, an LDPC decoder has a controller and one or more check-node units (CNUs). Each CNU is selectively configurable to operate in (i) a first mode that updates check-node (i.e., R) messages without averaging and (ii) a second mode that that updates R messages using averaging. Initially, each CNU is configured in the first mode to generate non-averaged R messages, and the decoder attempts to recover an LDPC-encoded codeword using the non-averaged R messages. If the decoder is unable to recover the correct codeword, then (i) the controller selects the averaging mode, (ii) each CNU is configured to operate in the second mode to generate averaged R messages, and (iii) the decoder attempts to recover the correct codeword using the averaged R messages. Averaging the R messages may slow down the propagation of erroneous messages that lead the decoder to convergence on trapping sets.

Abstract: Various embodiments of the present invention provide systems and methods for phase compensated harmonic sensing. For example, a circuit for harmonics calculation is disclosed that includes a phase difference estimation circuit and a phase offset compensation circuit. The harmonic calculation circuit is operable to calculate a first harmonic based on a periodic data pattern and a second harmonic based on the periodic data pattern. The phase difference estimation circuit operable to calculate a phase difference between the first harmonic and the second harmonic. The phase offset compensation circuit operable to align the second harmonic with the first harmonic to yield an aligned harmonic.

Abstract: Hardware-based methods and apparatus are provided for training high speed data links used in data transfer applications. A data valid window is calibrated on one or more high speed links by determining an offset delay value for at least one datapath using a finite state machine, wherein the offset delay value is based on a maximum offset delay value and a minimum offset delay value for the at least one datapath; and delaying a read data strobe signal based upon a base delay and the offset delay value for the at least one datapath. The offset delay value can be, for example, an average of the maximum offset delay and the minimum offset delay. The received pattern can be a predefined pattern or a programmable pattern. In addition, the received pattern can cover single-bit transitions and/or multi-bit transitions.

Abstract: A circuit breaker having a cradle, the circuit breaker comprises: an upper shutter and a lower shutter configured to open and close terminals of the cradle; an upper shutter operation link having one end connected to the upper shutter and another end rotatably coupled to a pivot; a lower shutter operation link having one end connected to the lower shutter and another end rotatably coupled to the pivot; and a shutter safety device comprising a coupling unit fixedly-coupled to the pivot, a rotation unit rotatably coupled to the coupling unit, and a link fixing unit provided at one end of the rotation unit, wherein the link fixing unit is to restrict rotation of the upper shutter operation link and the lower shutter operation link in a contacting manner.

Abstract: A mobile communications device Includes at least two long-range wireless Communications engines. Each long-range wireless communications engines includes a respectively different communications protocol stack, for receiving or transmitting first long-range wireless communications signals using a first long-range communications protocol simultaneously while receiving or transmitting second long-range wireless communications signals using a second long-range communications protocol At least two radio frequency blocks are provided, for receiving or transmitting the first long-range wireless signals simultaneously while receiving or transmitting the second long-range wireless signals. A user interface is provided for inputting and outputting user data Io and from the at least two long-range wireless communications engines, respectively.

Abstract: A pulse synchronizer circuit converts an input data signal generated under a source-clock domain into an output data signal under a destination-clock domain, where the destination clock is independent of the source clock. The pulse synchronizer circuit successfully converts each data pulse in the input data signal into a corresponding data pulse in the output data signal when the source clock is faster than the destination clock, when the source clock is slower than the destination clock, when an input data pulse has a duration of one source-clock cycle, and when an input data pulse has a duration of multiple source-clock cycles. The pulse synchronizer circuit has source-domain circuitry and destination-domain circuitry. The source-domain circuitry detects input data pulses and determines whether they are single- or multi-cycle data pulses. The destination-domain circuitry generates output data pulses based on the processing of the source-domain circuitry.

Abstract: Provided are an electronic switching device and a method for manufacturing the same. The electronic switching device includes a fixed unit including a fixed unit body defining an outer appearance thereof and a fixed contact part disposed within the fixed unit body, a movable unit including a movable contact part selectively contacting the fixed contact part to supply current, a moving part provided in the movable unit to guide a movement of the movable contact part toward the fixed contact part, a coil to which power is applied to move the moving part, and an elastic member that is elastically deformable while the moving part moves. At least one of the fixed unit and the moving part has a through hole so that an inner component of the fixed unit or the moving part communicates with the outside to allow a preset signal to pass therethrough.

Abstract: An electronic storage device includes a bit cell circuit, feedback circuit, and read accelerator circuit. The bit cell circuit is adapted for connection with true and complementary bit lines. The feedback circuit includes a first transistor which is coupled to a first voltage potential and responsive to the complementary bit line. The read accelerator circuit includes second, third, and fourth transistors coupled between the feedback circuit and a second voltage potential. The second transistor is responsive to a read line, the third transistor is responsive to the true bit line, and the fourth transistor is responsive to the complementary bit line. The read accelerator circuit is configured to provide a discharge path for at least one of the true bit line and the complementary bit line during a read access of the bit cell. Embodiments of a corresponding electronic read access accelerator device and method are also provided.

Abstract: Techniques are described for increasing a lifetime of a plurality of blocks of memory by equalizing a variation between the blocks. In operation, blocks to be written are allocated from a set of blocks having a lifetime factor below a threshold. The threshold is reset as required to resupply the set of blocks available for allocation.

Abstract: Disclosed is a travel velocity compensation apparatus for railway vehicles and a method thereof for compensating a travel velocity when there is generated a slide between a wheel and a railway, the apparatus including a velocity measurement unit measuring a travel velocity of a railway vehicle, a velocity estimation unit estimating the travel velocity using travel information of railway vehicle and rail information received from at least one sensor, a detection unit generating wheel slide information by determining whether wheels of the railway vehicle slide, using the travel velocity of the railway vehicle measured by the velocity measurement unit and the travel velocity estimated by the velocity estimation unit, and a selection unit selecting, as a travel velocity, any one of the travel velocity measured by the velocity measurement unit using the wheel slide information generated by the detection unit and the travel velocity estimated by the velocity estimation unit.

Abstract: Described embodiments provide a delay cell for a complementary metal oxide semiconductor integrated circuit. The delay cell includes a delay stage to provide an output signal having a programmable delay through the delay cell. The delay cell has a selectable delay value from a plurality of delay values and a selectable output skew value from a plurality of output skew values, where the cell size and terminal layout of the delay cell are relatively uniform for the plurality of delay values and the plurality of output skew values. The delay stage includes M parallel-coupled inverter stages of stacked PMOS transistors and stacked NMOS transistors. The stacked transistors have configurable source-drain connections between a drain and a source of each transistor, wherein the selectable delay value corresponds to a configuration of the configurable source-drain connections to adjust a delay value of each of the M inverter stages and an output skew value of the delay cell.

Abstract: Disclosed is a power factor correction circuit. The power factor correction circuit according to an exemplary embodiment of the present disclosure includes an electrolyte capacitor and a film capacitor, where ripple burden of the electrolyte capacitor is lessened to reduce the capacity of the condenser and to lengthen the life.

Abstract: Methods and structure are provided for implementing security features in SCSI Enclosure Services (SES) systems. The system comprises an SES device server, which includes a frontend interface, control unit, and backend interface. The frontend interface is operable to receive SES commands generated by Small Computer System Interface (SCSI) devices, and the backend interface is operable to manage operations of at least one peripheral device communicatively coupled with the SES device server based on received SES commands. The control unit is operable to determine whether a SCSI initiator that generated an SES command is an authorized device. The control unit is further operable to perform the SES command in response to determining that the SCSI initiator is an authorized device, and is further operable to reject the SES command in response to determining that the SCSI initiator is not an authorized device.

Abstract: A memory device includes a memory array comprising a plurality of memory cells, and control circuitry coupled to the memory array. The control circuitry comprises at least one dummy memory cell, a feedback-based controller having inputs coupled to respective internal nodes of the dummy memory cell, and write signal generation circuitry coupled to the feedback-based controller and configured to provide one or more write signals for controlling writing of data to portions of the memory array. The feedback-based controller generates a reset signal for application to a reset input of the write signal generation circuitry at least in part as a function of a logic level transition delay of a selected one of the first and second internal nodes of the dummy memory cell.

Abstract: Disclosed are an apparatus and a method for photovoltaic power generation according to the exemplary embodiment of the present disclosure configured to enhance efficiency of photovoltaic power generation, wherein the apparatus having a solar module, a booster and an inverter includes a voltage sensing unit configured to sense an output voltage of the solar module, a switching unit connected to the booster in parallel, and a controller configured to selectively control the booster or the switching unit whereby the booster or the switching unit can be driven in response to an output voltage level sensed by the voltage sensing unit.

Abstract: Methods and structure for accounting are provided for enhancing communications via a PCIE bridge. The bridge comprises a host interface that manages communications with a host device, and a PCIE interface that provides Memory Read Requests (MRds) to a PCIE device and receives Memory Read Completions (MRCs) from the PCIE device. The bridge also comprises a control unit that inserts tag information into the MRds. The control unit detects a reset of the host interface and revises the tag information inserted into the MRds responsive to detecting the reset. Additionally, the control unit analyzes tag information of received MRCs to determine whether it is the revised tag information or is old tag information, returns completion data from MRCs having the revised tag information to the host device, and discards completion data from received MRCs having the old tag information.

Abstract: An apparatus comprising a controller, one or more host devices and one or more storage devices. The controller may be configured to store and/or retrieve data in response to one or more input/output requests. The one or more host devices may be configured to present the input/output requests. The one or more storage devices may be configured to store and/or retrieve the data. The controller may include a cache memory configured to store the input/output requests. The cache memory may be configured as a memory allocation table to store and/or retrieve a compressed version of a portion of the data in response to one or more network parameters. The compressed version may be retrieved from the memory allocation table instead of the storage devices based on the input/output requests to improve overall storage throughput.

Abstract: A compensation circuit for controlling a variation in output impedance of at least one buffer circuit includes a monitor circuit and a control circuit coupled with the monitor circuit. The monitor circuit includes a pull-up portion including at least one PMOS transistor and a pull-down portion comprising at least one NMOS transistor. The monitor circuit is configured to track an operation of an output stage of the buffer circuit and is operative to generate at least a first control signal indicative of a status of at least one characteristic of corresponding pull-up and pull-down portions in the output stage of the buffer circuit over variations in PVT conditions to which the buffer circuit may be subjected. The control circuit is operative to generate a set of digital control bits as a function of the first control signal. The set of digital control bits is operative to compensate the pull-up and pull-down portions in the output stage of the buffer circuit over prescribed variations in PVT conditions.

Abstract: In described embodiments, a timestamp generator includes a fixed clock domain driven by a fixed frequency clock, a core clock domain, coupled to the fixed clock domain, which is driven by a core clock whose frequency is adjustable during an operation of the timestamp generator. A timestamp logic operating in the core clock domain generates a timestamping output of the timestamp generator. A rate generator operating in both the fixed clock domain and the core clock domain generates per clock cycle increments in the fixed clock domain and transfers carry units from the fixed clock domain into the core clock domain, and a timestamp increment generation of the timestamp logic is clocked by the fixed frequency clock provided by the rate generator. A method for enabling timestamp in an ASIC to be accurate with system clock changes is also described.

Abstract: Described embodiments provide an apparatus for calculating an N-point discrete Fourier transform of an input signal having multiple sample values. The apparatus includes at least one input configured to receive the sample values and a counter to count sample periods. Also included are at least two parallel multipliers to multiply each sample value, with each of the multipliers having a corresponding multiplication factor. There is at least one multiplexer to select one of the at least two parallel multipliers. An adder sums the scaled sample values and an accumulator accumulates the summed sample values. N is an integer and the at least two parallel multipliers are selectable based upon the value of N and the value of the sample period count.