Abstract: Methods and apparatus are provided for encoding and decoding in flash memories using convolutional-type low parity density check codes. A plurality of bits to be stored on a flash memory device are encoded using a convolutional-type low density parity check code, such as a spatially coupled low density parity check code. The encoded pages or portions thereof can be decoded independently of other pages. In one embodiment, an encoded page is decoded jointly with one or more additional pages in the same wordline or a different wordline.

Abstract: An interface device to interface a processing device and a memory device includes an error correcting code (ECC) encoder to calculate ECC bit(s) and to provide the ECC bit(s) to the processing device based at least in part on data provided by the memory device, thereby eliminating a need to store the ECC bits in the memory device. The interface device may include a parity encoder to provide parity bit(s) to the memory device as a function of data provided by the processing device, and a parity decoder to selectively modify the ECC bit(s) as a function of the data and parity bit(s) provided by the memory device. The ECC encoder may provide ECC bits, and the parity decoder may selectively modify the ECC bits provided to the processing device based on data provided by the memory device and parity bit(s) provided by the memory device.

Abstract: Lighting apparatus and structures are described to space electrical drivers from a light panel. In this way, a driver box housing the driver can be spaced from the light panel to communicate with pre-existing facilities (e.g. electrical wiring) and can serve the additional advantage of keeping the driver box out of standing water that may accumulate on the structure.

Abstract: Described embodiments process data packets received by a switch coupled to a network processor. The switch determines whether one or more rules for classifying and processing the received packet are stored in an internal classification database of the switch. If one or more rules are stored in the internal database, the switch updates statistics corresponding to each of the rules and classifies and processes the received packet in accordance with the rules. If no associated rules are stored in the internal database, the switch tags the received packet with metadata and forwards the packet to the network processor. The network processor determines one or more rules for classifying and processing the forwarded packet in a classification database of the network processor and updates statistics corresponding to each rule. The network processor classifies and processes the packet in accordance with the rules and updates the internal database of the switch.

Abstract: A tiered data storage system having a cache employs a tiering management subsystem to analyze data access patterns over time, and a cache management subsystem to monitor individual input/output operations and replicate data in the cache. The tiering management subsystem determines a distribution of data between tiers and determines what data should be cached while the cache management subsystem moves data into the cache. The tiered data storage system may analyze individual input/output operations to determine if data should be consolidated from multiple regions in one or more data storage tiers into a single region.

Abstract: A lighted architectural mesh includes a plurality of interconnected wires forming a plurality of transverse openings. At least one light carrier is slidably received within at least one of said transverse openings. The at least one light carrier includes light nodes emitting light through the interstices on the front and/or rear side of the architectural mesh. The at least one light carrier further comprises a plurality of connecting elements, wherein the light emitter nodes of the at least one light element are releasably interconnected in series by the connecting elements.

Abstract: Methods and apparatus are provided for detection and decoding in flash memories with selective binary and non-binary decoding. Data from a flash memory device is processed by obtaining one or more read values for a plurality of bits from one or more pages of the flash memory device; converting; the one or more read values for the plurality of bits to a non-binary log likelihood ratio based on a probability that a given data pattern was written to the plurality of bits when a particular pattern was read from the plurality of bits; and jointly decoding the plurality of bits using the non-binary log likelihood ratio, wherein the pages are encoded independently.

Abstract: An input circuit in high speed counter module for PLC is provided, the input circuit being configured such that various types of pulse signals are changed to a single type of pulse signal and transmitted to an MPU, whereby the type of input pulse is checked or an operation of checking addition/deduction is omitted to increase an interrupt process speed.

Abstract: A power transmission apparatus according to an embodiment of the present invention can improve the reliability of an opening operation of the high voltage LBS by using both a main circuit opening driving force of an opening spring and an opening driving force from an actuator mechanism. The power transmission apparatus comprises a main circuit opening power transmission mechanism for transmitting an opening position rotating power of a power transmission shaft to the main circuit switch in order to move the main circuit switch to an opening position.

Abstract: An adaptive filter implemented in a communication system transmitter or receiver has a real time clock associated therewith, and one or more coefficients of the adaptive filter are determined based at least in part on an output of the real time clock. For example, the adaptive filter may comprise a coefficient update engine and a memory for storing a plurality of sets of adaptive filter coefficients in association with respective time indicators derived from the output of the real time clock, with the coefficient update engine being configured to determine a particular one of the sets of filter coefficients for use by the adaptive filter based at least in part on one or more of the time indicators. The time indicators may comprise respective time stamps generated based on the output of the real time clock at respective times at which the corresponding sets of coefficients are determined.

Abstract: In described embodiments, a transceiver supports two or more rates using an oversampling clock and data recovery (CDR) circuit sampling high rate data with a predetermined CDR sampling clock. A timing recovery circuit detects and accounts for extra or missing samples when oversampling lower rate data. An edge detector detects each actual data symbol edge and provides for an edge decision offset in a current instant's block of samples. An edge error is generated from the previous instant's actual and calculated edges; and an edge distance between actual edges of the current and previous instants is generated. Filtered edge distance and error are combined to generate a calculated edge position for the data symbol edge for the current instant. The edge decision offset is applied to the current calculated edge position to identify a sample value to generate a decision for the data symbol to detect the current data value.

Abstract: Described embodiments provide a host subsystem that generates a host context corresponding to a received host data transfer request. A programmable sequencer generates one or more sequencer contexts based on the host context. Each of the sequencer contexts corresponds to at least part of the host data transfer request. The sequencer contexts are provided to a buffer subsystem of the media controller. For host read requests, the buffer subsystem retrieves the data associated with the sequencer contexts of the read request from a corresponding buffer or a storage media and transmits the data associated with the sequencer contexts to the host device. For host write requests, the buffer subsystem receives the data associated with the host context from the host device and stores the data associated with the sequencer contexts of the write request to a corresponding buffer or the storage media.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, a method for data processing is disclosed that includes receiving a codeword that has at least a first circulant with a plurality of data bits and a first circulant parity bit, a second circulant with a plurality of data bits and a second circulant parity bit, and one or more codeword parity bits. The methods further include decoding the codeword using the one or more codeword parity bits to access the first circulant and the second circulant, performing a first circulant parity check on the first circulant, and performing a second circulant parity check on the second circulant.

Abstract: Various embodiments of the present invention provide systems and methods for locating a reference pattern on a storage medium. For example, various embodiments of the present invention provide systems for locating a reference pattern on a storage medium. Such systems include a sliding window phase calculator circuit, a delay circuit and a mark detector circuit.

Abstract: Disclosed is a method and device for concurrently performing a plurality of data manipulation operations on data being transferred via a Direct Memory Access (DMA) channel managed by a DMA controller/engine. A Control Data Block (CDB) that controls where the data is retrieved from, delivered to, and how the plurality of data manipulation operations are performed may be fetched by the DMA controller. A CDB processor operating within the DMA controller may read the CDB and set up the data reads, data manipulation operations, and data writes in accord with the contents of the CDB. Data may be provided from one or more sources and data/modified data may be delivered to one or more destinations. While data is being channeled through the DMA controller, the DMA controller may concurrently perform a plurality of data manipulation operations on the data, such as, but not limited to: hashing, HMAC, fill pattern, LFSR, EEDP check, EEDP generation, XOR, encryption, and decryption.

Abstract: Various embodiments of the present invention provide systems and methods for selecting data encoding. As an example, some embodiments of the present invention provide methods that include receiving a data set to be written to a plurality of multi-bit memory cells that are each operable to hold at least two bits. In addition, the methods include determining a characteristic of the data set, and encoding the data set. The level of encoding is selected based at least in part on the characteristic of the data set. In some instances of the aforementioned embodiments, the characteristic of the data set indicates an expected frequency of access of the data set from the plurality of multi-bit memory cells.

Abstract: In one embodiment, an LDPC decoder performs a targeted bit adjustment method to recover a valid codeword after the decoder has failed. In a first stage, a post processor initializes the decoder by saturating LLR values output by the decoder during the last (i.e., failed) iteration to a relatively small value. Then, two-bit trials are performed, wherein LLR values corresponding to two bits of the codeword are adjusted in each trial. Decoding is performed with the adjusted values, and if the number of unsatisfied check nodes exceeds a specified threshold, then a second stage is performed. The post processor initializes the decoder by saturating the LLR values output by the decoder during the last (i.e., failed) iteration of the first stage to a relatively small value. The second stage then performs single-bit adjustment trials, wherein one LLR value corresponding to one bit of the codeword is adjusted in each trial.

Abstract: Methods and structure for automated determination and reconfiguration of the size of a cache memory in a storage system. Features and aspects hereof generate historical information regarding frequency of hits on cache lines in the cache memory. The history maintained is then analyzed to determine a desired cache memory size. The historical information regarding cache memory usage may be communicated to a user who may then direct the storage system to reconfigure its cache memory to a desired cache memory size. In other embodiments, the storage system may automatically determine the desired cache memory size and reconfigure its cache memory. The method may be performed automatically periodically, and/or in response to a user's request, and/or in response to detecting thrashing caused by least recently used (LRU) cache replacement algorithms in the storage system.

Abstract: The present disclosure provides a magnetic coil assembly for suppressing the generation of broken wire in a coil as well as reducing a winding time, the magnetic coil assembly according to the present disclosure comprise a bobbin; a magnetic coil wound around the bobbin; a pair of terminals fixedly installed at the bobbin; a first coil fixing protrusion portion extended from the terminal to fix a starting end portion of a first coil half which is a half of the entire length of the magnetic coil; a second coil fixing protrusion portion extended from the bobbin to fix a starting end portion of a second coil half which is the remaining half of the magnetic coil, and fix an terminal end portion of the first coil half; and a third coil fixing protrusion portion extended from the terminal to fix a terminal end portion of the second coil half.

Abstract: A data-duplicating expander device attachable to a storage topology and a method. The data-duplicating expander device may include a direct-attached SAS expander configured for direct duplication of data from source disks to destination disks by bypassing transfer to or from a host system. The device may include dedicated expander phys and a processor. The device may be configured to receive instructions from an initiator storage-topology-connected device to configure or start a data transfer. The data-duplicating expander device may be configured to receive source data from source disks by utilizing dedicated expander phys and may be configured to transfer destination data directly and simultaneously to the destination disks by utilizing dedicated expander phys, said destination data being associated with the source data. Directly transferring destination data bypasses transfer of the source data or the destination data to or from a host system.