Abstract: An optical disk playback device comprises first and second lasers, an optical assembly, first and second optical detectors, and controller circuitry coupled to the optical detectors. The optical assembly is configured to direct incident light from the first and second lasers so as to form respective leading and trailing scanning spots on a surface of an optical disk, and is further configured to direct corresponding reflected light from the leading and trailing scanning spots on the surface of the optical disk to respective ones of the optical detectors. The controller circuitry is configured to identify a surface imperfection of the optical disk by processing the reflected light associated with the leading scanning spot prior to the trailing scanning spot reaching that surface imperfection.

Abstract: An apparatus including a first circuit and a second circuit. The first circuit may be configured to determine values for a predefined metric for a plurality of tap positions within a range covered by a decision feedback equalizer (DFE). The values for a number of taps may be determined in parallel. The second circuit may be configured to set one or more floating taps of the DFE to tap positions based upon the values of the predefined metric. The floating taps in the decision feedback equalizer may be selected adaptively.

Abstract: A data storage system includes a first server including: a first plurality of storage disks configured to store data, and a first host bus adapter including a first processor configured to provide a first virtual expander and a first logic component; and a second server including: a second plurality of storage disks configured to store data, and a second host bus adapter including a second processor configured to provide a second virtual expander and a second logic component, wherein the first host bus adapter of the first server is coupled to the second host bus adapter of the second server via a SAS connection, and wherein each of the first plurality of storage disks and the second plurality of storage disks are accessible by each of the first server and the second server.

Abstract: Recursive digital pre-distortion (DPD) techniques are provided. Digital pre-distortion is performed by applying a signal to a recursive system to generate a state vector; providing the state vector as a feedback value to the recursive non-linear system; and applying the state vector to a second function to generate an output signal, wherein at least one of the recursive system and the second function comprise a non-linear function. The recursive non-linear system can be initialized to a known initial value. The recursive system is defined by a system of non-linear differential equations.

Abstract: An outage schedule management apparatus and a method are provided, wherein a topology change is executed in response to an outage schedule set up by a user input, and a validity determination is executed to system operation standard to approve an outage.

Abstract: Crest factor reduction (CFR) techniques are provided using asymmetrical pulses. A crest factor reduction method comprises obtaining one or more data samples; detecting at least one peak in the one or more data samples; performing peak cancellation on the at least one detected peak by applying an asymmetric cancellation pulse to the at least one detected peak: and providing processed versions of the one or more data samples. The asymmetric cancellation pulse is generated, for example, by a minimum phase filter and has a substantially minimum group delay. New peaks associated with peak re-growth are introduced substantially only to the one side of the asymmetric cancellation pulse. The process can optionally rewind by an amount greater than or substantially equal to a group delay of the asymmetric cancellation pulse to address the limited number of pre-cursors that may be present in the asymmetric cancellation pulse.

Abstract: An apparatus, system, and method for upgrading firmware of an energy metering device are provided. A method for upgrading firmware of an energy metering device which receives firmware from a server via a network and upgrade firmware includes: transmitting a size of a firmware segment to the server, initializing firmware upgrade, receiving a firmware segment from the server, and controlling the energy metering device to operate with received firmware in response to a request for activating firmware from the server. The server communicates with the energy metering device by using an object model obtained by object-modeling the size of a firmware segment, the firmware segment download, and the activation request.

Abstract: Software implementations are provided for performing IQ imbalance correction and/or RF equalization. An input signal, x, is processed in software by executing a vector convolution instruction to apply the input signal, x, to a first complex FIR filter that performs one or more of RF equalization and IQ imbalance correction; and executing a vector convolution instruction to apply a conjugate x* of the input signal, x, to a second complex FIR filter that performs the one or more of RF equalization and IQ imbalance correction, wherein the second complex FIR filter is in parallel with the first complex FIR filter. The first and second complex FIR filters have complex coefficients and the input signal comprises a complex signal.

Abstract: The present invention is directed to a method for completing a stripe write operation in a timely fashion to a RAID drive pool which includes an abnormally slow drive. For example, the stripe write operation either completes within a required time interval, or an error is provided to the host/initiator which provides an indication to an application that the stripe write operation did not complete.

Abstract: Multi-stage crest factor reduction (CFR) techniques are provided for multi-channel multi-standard radio (MSR). A multi-stage crest factor reduction method comprises applying one or more data samples associated with at least one channel of a first technology type to a first individual crest factor reduction block; applying one or more data samples associated with at least one channel of a second technology type to a second individual crest factor reduction block; aggregating outputs of the first and second individual crest factor reduction blocks to generate an aggregated output; and applying the aggregated output to a composite crest factor reduction block. The individual crest factor reduction blocks can be implemented using a sampling rate appropriate for the corresponding technology type. The composite crest factor reduction block operates at a higher sampling rate than the individual crest factor reduction blocks.

Abstract: The present invention is directed to a method for pre-emptive read reconstruction. In the method(s) disclosed herein, when a pre-emptive read reconstruction timer times out, if one or more drive read operations for providing requested stripe read data are still pending; and if stripe read data corresponding to the pending drive read operations may be constructed (ex.—reconstructed) based on the stripe read data received before the expiration of the timer, the pending drive read operations are classified as stale, but the pending drive read operations are still allowed to complete rather than being aborted, thereby promoting efficiency of the data storage system in situations when the data storage system includes an abnormal disk drive (ex.—a disk drive which endures random cycles of low read performance).

Abstract: Described embodiments provide a network processor that includes a security protocol processor to prevent replay attacks on the network processor. A memory stores security associations for anti-replay operations. A pre-fetch module retrieves an anti-replay window corresponding to a data stream of the network processor. The anti-replay window has a range of sequence numbers. When the network processor receives a data packet, the security hardware accelerator determines a value of the received sequence number with respect to minimum and maximum values of a sequence number range of the anti-replay window. Depending on the value, the data packet is either received or accepted. The anti-replay window might be updated to reflect the receipt of the most recent data packet.

Abstract: A lighting apparatus having a base member and a directional member are shown and described. The base member includes a first surface having a plurality of reflective elements extending therefrom. The base member also including a plurality of openings arranged in a pattern. Each openings is configured to receive a respective light source. The directional member has a portion of a reflective surface positioned relative to at least one opening to reflect light radiating from a lighting source disposed within the opening towards a portion of at least one of the reflective elements extending from the base member.

Abstract: Data latch circuit and method of low power decision feedback equalization (DFE) system is disclosed. In one embodiment, the data latch circuit of the of a decision feedback equalization (DFE) system includes a first parallel n-channel metal-oxide-semiconductor field-effect transistor (NMOS) pair to input a differential input voltage. The data latch circuit also includes a second parallel NMOS pair coupled to the first parallel NMOS pair to input a decision feedback equalization (DFE) voltage. The data latch circuit further includes a cross-coupled PMOS pair to generate a positive feedback to the first parallel NMOS pair and/or the second parallel NMOS pair. In addition, the data latch circuit includes a cross-coupled NMOS pair to escalate the positive feedback. Furthermore the data latch circuit includes a latching circuit to generate a signal data based on the sinking of a current at an input of the latching circuit and/or the positive feedback.

Abstract: Described embodiments provide an apparatus for calculating an N-point discrete Fourier transform of an input signal having multiple sample values. The apparatus includes at least one input configured to receive the sample values and a counter to count sample periods. Also included are at least two parallel multipliers to multiply each sample value, with each of the multipliers having a corresponding multiplication factor. There is at least one multiplexer to select one of the at least two parallel multipliers. An adder sums the scaled sample values and an accumulator accumulates the summed sample values. N is an integer and the at least two parallel multipliers are selectable based upon the value of N and the value of the sample period count.

Abstract: A method of motion estimation (ME) refinement. The method generally includes the steps of (A) generating an initial motion vector (MV) by conducting a first ME on an initial block in a picture, the initial block covering an initial area of the picture, (B) generating a current MV by conducting a second ME on a current block in the picture, (i) the current block covering a subset of the initial area and (ii) the second ME being seeded by the initial MV, (C) generating at least one additional MV by conducting at least one third ME on the current block, the at least one third ME being seeded respectively by at least one neighboring MV spatially adjacent to the current MV and (D) generating a refined MV of the current block by storing in a memory a best among the current MV and the additional MV.

Abstract: A power supply system for EV and a control method thereof are provided, the system including a high voltage battery generating a driving voltage to a motor of the EV, a low voltage battery generating a driving voltage for other electronic equipment, an LDC (low voltage DC-DC Converter) converting a high voltage generated by the high voltage battery to a low voltage, and generating a control power for charging the low voltage battery, an alternator generating a control power for charging the low voltage battery using a rotary power of the motor, and a control power selector selectively supplying the control power generated by the LDC or the alternator to the low voltage battery.

Abstract: A luminaire is disclosed comprising one or more side members having one or more light modules associated therewith and defining a recess. The light module having one or more light sources, one or more light directing members, and a lens enclosing the light sources and directing members in the module. The light directing members can comprise reflector modules of different configurations to provide different light distributions from the associated one or more light sources. The light modules can be configured to cast different light distributions to combine to form the desired light distribution. The light modules can be designed or exchanged to create any desired light distribution from the same side members. The light module can comprise a tray such that the lens is sealed to the tray keeping moisture from entering the module.

Abstract: An apparatus for estimating rotor time constant of induction motor, the apparatus being such that d-axis and q-axis current commands are received to output q-axis voltage command, to output q-axis voltage estimate, to output a changed value of rotor time constant, which is a difference between the q-axis voltage command and the q-axis voltage estimate, and to add the changed value of the rotor time constant to a rotor time constant, whereby the changed rotor time constant is outputted.

Abstract: The present invention provides methods and apparatus for accomplishing optical direct write phase shift lithography. A lithography system and method are provided wherein a mirror array is configured to generate vortex phase shift optical patterns that are directed onto a photosensitive layer of a substrate. The lithography methods and systems facilitate pattern transfer using such vortex phase shift exposure patterns.